Integer_File.v.bak

// msrv32_integer_file 21BCE0289
module Integer_File(ms_riscv32_mp_clk_in, ms_riscv32_mp_rst_in, rs_2_addr_in, rd_addr_in, wr_en_in, rd_in, rs_1_addr_in, rs_1_out, rs_2_out);
	input ms_riscv32_mp_clk_in;
	input ms_riscv32_mp_rst_in;
	input [4:0] rs_2_addr_in;
	input [4:0] rd_addr_in;
	input wr_en_in;
	input [31:0] rd_in;
	input [4:0] rs_1_addr_in;
	output [31:0] rs_1_out;
	output [31:0] rs_2_out;

	reg signed [31:0] reg_file [31:0];
	integer i;

	initial begin
		reg_file[0] = 0;			// no write operations allowed for reg_file[0]
		for (i=1; i<32; i=i+1) begin
			reg_file[i] = 0;
		end
	end
	
	always @(posedge ms_riscv32_mp_clk_in or posedge ms_riscv32_mp_rst_in) begin
		if ((wr_en_in) && (rd_addr_in != 0) && (rs_1_addr_in != rd_addr_in) && (rs_2_addr_in != rd_addr_in)) begin
			reg_file[rd_addr_in] = rd_in;
		end
		if (ms_riscv32_mp_rst_in) begin
			for (i=1; i<32; i=i+1) begin
				reg_file[i] = 0;
			end
		end
	end

	assign rs_1_out = ((rs_1_addr_in == rd_addr_in) & (wr_en_in == 1)) ? rd_in : reg_file[rs_1_addr_in];
	assign rs_2_out = ((rs_2_addr_in == rd_addr_in) & (wr_en_in == 1)) ? rd_in : reg_file[rs_2_addr_in];
endmodule