Reg_Block_1_tb.v

// Testbench for msrv32_reg_block_1 21BCE0289
module Testbench_Reg_Block_1;
	reg [31:0] pc_mux_in;
	reg ms_riscv32_mp_clk_in;
	reg ms_riscv32_mp_rst_in;
	wire [31:0] pc_out;
	
	msrv32_reg_block_1 Reg_Block_1(
		.pc_mux_in(pc_mux_in),
		.ms_riscv32_mp_clk_in(ms_riscv32_mp_clk_in),
		.ms_riscv32_mp_rst_in(ms_riscv32_mp_rst_in),
		.pc_out(pc_out)
	);
	
	always begin
		#5 ms_riscv32_mp_clk_in = ~ms_riscv32_mp_clk_in;
	end

	initial begin
		ms_riscv32_mp_clk_in = 0;
		pc_mux_in = 32'h00000011;
		ms_riscv32_mp_rst_in = 0;
		
		#20;

		pc_mux_in = 32'h00000022;
		
		#15;

		pc_mux_in = 32'h00000033;
		ms_riscv32_mp_rst_in = 1;

		#10;

		ms_riscv32_mp_rst_in = 0;
		pc_mux_in = 32'h00000099;

		#25;

		$stop;
	end

	always @(posedge ms_riscv32_mp_clk_in) begin
		$display("pc_out: %h", pc_out);
	end
endmodule