Store_Unit_tb.v.bak

// Testbench for msrv32_store_unit 21BCE0289
module Testbench_Store_Unit;
	reg [1:0] funct3_in;
	reg [31:0] iadder_in;
	reg [31:0] rs2_in;
	reg mem_wr_req_in;
	reg ahb_ready_in;
	wire [31:0] ms_riscv32_mp_dmdata_out;
	wire [31:0] ms_riscv32_mp_dmadder_out;
	wire [3:0] ms_riscv32_mp_dmwr_mask_out;
	wire ms_riscv32_mp_dmwr_req_out;
	wire [1:0] ahb_htrans_out;

	Store_Unit msrv32_store_unit(
		.funct3_in(funct3_in),
		.iadder_in(iadder_in),
		.rs2_in(rs2_in),
		.mem_wr_req_in(mem_wr_req_in),
		.ahb_ready_in(ahb_ready_in),
		.ms_riscv32_mp_dmdata_out(ms_riscv32_mp_dmdata_out),
		.ms_riscv32_mp_dmadder_out(ms_riscv32_mp_dmadder_out),
		.ms_riscv32_mp_dmwr_mask_out(ms_riscv32_mp_dmwr_mask_out),
		.ms_riscv32_mp_dmwr_req_out(ms_riscv32_mp_dmwr_req_out),
		.ahb_htrans_out(ahb_htrans_out)
	);

	initial begin
		funct3_in = 2'b00;
		iadder_in = 32'h00000002;
		rs2_in = 32'h87654321;
		mem_wr_req_in = 1;
		ahb_ready_in = 0;
		#10;

		ahb_ready_in = 1;
		#10;

		funct3_in = 2'b10;
		iadder_in = 32'hfffffff1;
		#10;

		$stop;
	end
endmodule