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SamulKyullSamulKyull
SamulKyull
authored and
SamulKyull
committed
Merge branch 'avaota-m1'
2 parents 6a40dfe + 792d165 commit 55824ee

8 files changed

Lines changed: 227 additions & 52 deletions

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‎board/avaota-m1/CMakeLists.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,4 +5,8 @@ set(APP_COMMON_SOURCE
55
${CMAKE_CURRENT_SOURCE_DIR}/head.c
66
)
77

8+
set(APP_LINK_LIBRARY
9+
${CMAKE_CURRENT_SOURCE_DIR}/../lib/libdram.a
10+
)
11+
812
add_subdirectory(hello_world)

‎board/avaota-m1/board.c‎

Lines changed: 42 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -102,40 +102,50 @@ sunxi_sdhci_t sdhci0 = {
102102
};
103103

104104
uint32_t dram_para[128] = {
105-
2400, // dram_clk
106-
9, // dram_type
107-
0x0e0e0e0e,// dram_dx_odt
108-
0x0f0f0f0f,// dram_dx_dri
109-
0xec030e0f,// dram_ca_dri
110-
0, // dram_para0
111-
0xa10a, // dram_para1
112-
0x1001, // dram_para2
113-
0, // dram_mr0
114-
0, // dram_mr1
115-
0, // dram_mr2
116-
0x6, // dram_mr3
117-
0, // dram_mr4
118-
0, // dram_mr5
119-
0, // dram_mr6
120-
0x12, // dram_mr11
121-
0x44, // dram_mr12
122-
0, // dram_mr13
123-
0x34, // dram_mr14
124-
0, // dram_mr16
125-
0x06, // dram_mr17
126-
0, // dram_mr22
127-
0x4040, // dram_tpr0
128-
0, // dram_tpr1
129-
0x170b070, // dram_tpr2
130-
0x3800, // dram_tpr3
131-
0x3514, // dram_tpr6
132-
0x325f0000,// dram_tpr10
133-
0, // dram_tpr11
134-
0, // dram_tpr12
135-
0x10061, // dram_tpr13
136-
0 // dram_tpr14
105+
1008, // dram_clk
106+
8, // dram_type
107+
0x07070707,// dram_dx_odt
108+
0x0C0C0C0C,// dram_dx_dri
109+
0x0C0C0C, // dram_ca_dri
110+
0x59595B5D,// dram_para0
111+
0x310a, // dram_para1
112+
0x01000, // dram_para2
113+
0x0, // dram_mr0
114+
0x0, // dram_mr1
115+
0x0, // dram_mr2
116+
0x33, // dram_mr3
117+
0x3, // dram_mr4
118+
0x0, // dram_mr5
119+
0x0, // dram_mr6
120+
0x66, // dram_mr11
121+
0x30, // dram_mr12
122+
0x0, // dram_mr13
123+
0x20, // dram_mr14
124+
0x0, // dram_mr16
125+
0x0, // dram_mr17
126+
0x2, // dram_mr22
127+
0, // dram_tpr0
128+
0x28282828,// dram_tpr1
129+
0, // dram_tpr2
130+
0, // dram_tpr3
131+
0x103F353F,// dram_tpr6
132+
0x00004B00,// dram_tpr10
133+
0x65656667,// dram_tpr11
134+
0x18161718,// dram_tpr12
135+
0x00000051,// dram_tpr13
136+
0x010701f5 // dram_tpr14
137137
};
138138

139+
int sunxi_nsi_init(void) {
140+
writel(0x40005, 0x2402C00 + 0x6c);
141+
writel(0xFF, 0x2402600 + 0x14);
142+
writel(0xFF, 0x2402800 + 0x14);
143+
writel(0xFF, 0x2402a00 + 0x14);
144+
writel(0x1, 0x2400000 + 0xc);
145+
writel(0x1, 0x2400200 + 0xc);
146+
return 0;
147+
}
148+
139149
void neon_enable(void) {
140150
/* Set the CPACR for access to CP10 and CP11*/
141151
asm volatile("LDR r0, =0xF00000");
@@ -146,14 +156,6 @@ void neon_enable(void) {
146156
asm volatile("MCR p10, 7, r3, c8, c0, 0");
147157
}
148158

149-
typedef enum {
150-
SUNXI_SOC_VER_INVALID = -1,
151-
SUNXI_SOC_VER_A = 0,
152-
SUNXI_SOC_VER_B = 1,
153-
SUNXI_SOC_VER_C = 2,
154-
} sunxi_soc_version_t;
155-
156-
157159
void clean_syterkit_data(void) {
158160
/* Disable MMU, data cache, instruction cache, interrupts */
159161
arm32_mmu_disable();

‎board/avaota-m1/hello_world/main.c‎

Lines changed: 88 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,6 @@ extern sunxi_sdhci_t sdhci0;
2727

2828
extern uint32_t dram_para[128];
2929

30-
extern int init_DRAM(int type, void *buff);
31-
3230
msh_declare_command(bt);
3331
msh_define_help(bt, "backtrace test", "Usage: bt\n");
3432
int cmd_bt(int argc, const char **argv) {
@@ -51,11 +49,99 @@ const msh_command_entry commands[] = {
5149
msh_command_end,
5250
};
5351

52+
static void sunxi_res_ctrl_init(void) {
53+
uint8_t reg_val;
54+
55+
reg_val = readl(SID_RES0_1_BASE) >> 24;
56+
if ((reg_val & 0xFF) == 0)
57+
return;
58+
59+
uint8_t res0_val = (reg_val >> 0) & 0xF;
60+
writel((0x19190000 | (res0_val & 0xF)), INT_DSI_RES_CTRL_REG);
61+
writel((0x19190000 | res0_val), INT_CSI_RES_CTRL_REG);
62+
writel((0x19190000 | res0_val), INT_USB_RES_CTRL_REG);
63+
64+
uint8_t res1_val = (reg_val >> 4) & 0xF;
65+
writel((0x19190000 | res1_val), INT_EDP_RES_CTRL_REG);
66+
writel((0x19190000 | res1_val), INT_HS_COMBO_RES_CTRL_REG);
67+
writel((0x19190000 | res1_val), INT_DDR_RES_CTRL_REG);
68+
69+
return;
70+
}
71+
72+
static void sunxi_board_power_init(void) {
73+
uint32_t sys_vol, gpu_vol;
74+
uint32_t efuse;
75+
uint32_t efuse_ext;
76+
77+
efuse = (readl(SUNXI_SID_BASE + 0x200 + 0x14) & 0xff0000) >> 16;
78+
efuse_ext = (readl(SUNXI_SID_BASE + 0x200 + 0x14) & 0xff000000) >> 24;
79+
if (efuse_ext) {
80+
efuse = efuse_ext;
81+
}
82+
83+
switch (efuse) {
84+
/* VF0/VF4-2/VF3: sys-0.9v gpu-0.94v */
85+
case 0x00:
86+
case 0x24:
87+
case 0x03:
88+
sys_vol = 900;
89+
gpu_vol = 940;
90+
break;
91+
/* VF1/VF4-4: sys-0.9v gpu-0.9v */
92+
case 0x01:
93+
sys_vol = 900;
94+
gpu_vol = 980;
95+
break;
96+
case 0x44:
97+
sys_vol = 900;
98+
gpu_vol = 900;
99+
break;
100+
/* VF4-3: sys-0.92v gpu-0.96v */
101+
case 0x34:
102+
sys_vol = 920;
103+
gpu_vol = 960;
104+
break;
105+
/* default: sys-0.9v gpu-0.94v */
106+
default:
107+
sys_vol = 900;
108+
gpu_vol = 940;
109+
break;
110+
}
111+
112+
sunxi_i2c_init(&i2c_pmu);
113+
114+
pmu_axp2202_init(&i2c_pmu);
115+
pmu_axp1530_init(&i2c_pmu);
116+
117+
if (readl(SUNXI_SOC_VER_REG) & SUNXI_SOC_VER_MASK < 2)
118+
sys_vol = gpu_vol;
119+
120+
pmu_axp2202_set_vol(&i2c_pmu, "dcdc1", 1050, 1);
121+
pmu_axp2202_set_vol(&i2c_pmu, "dcdc2", sys_vol, 1);
122+
123+
pmu_axp1530_set_vol(&i2c_pmu, "dcdc1", 1000, 1);
124+
pmu_axp1530_set_vol(&i2c_pmu, "dcdc2", 1000, 1);
125+
pmu_axp1530_set_vol(&i2c_pmu, "dcdc3", gpu_vol, 1);
126+
127+
/* dcdc4 for 3v3 */
128+
pmu_axp2202_set_vol(&i2c_pmu, "dcdc4", 3300, 1);
129+
130+
/* bldo3 for 1v8 */
131+
pmu_axp2202_set_vol(&i2c_pmu, "bldo3", 1800, 1);
132+
}
133+
54134
int main(void) {
55135
sunxi_serial_init(&uart_dbg);
56136

137+
sunxi_res_ctrl_init();
138+
57139
show_banner();
58140

141+
sunxi_board_power_init();
142+
143+
sunxi_dram_init(dram_para);
144+
59145
syterkit_shell_attach(commands);
60146

61147
abort();

‎cmake/board/avaota-m1.cmake‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,10 @@ set(CONFIG_ARCH_ARM32_ARM64 True)
55
set(CONFIG_CHIP_SUN65IW1 True)
66
set(CONFIG_CHIP_WITHPMU True)
77
set(CONFIG_CHIP_DCACHE True)
8+
set(CONFIG_CHIP_MMC_V2 True)
89
set(CONFIG_CHIP_GPIO_V4 True)
910
set(CONFIG_BOARD_AVAOTA_M1 True)
1011

11-
set(CONFIG_CHIP_MINSYS True)
12-
1312
add_definitions(-DCONFIG_CHIP_SUN65IW1)
1413
add_definitions(-DCONFIG_CHIP_DCACHE)
1514
add_definitions(-DCONFIG_CHIP_MMC_V2)

‎include/drivers/chips/sun65iw1/reg-ncat.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,4 +195,18 @@
195195

196196
#define SUNXI_SID_SRAM_BASE (SUNXI_SID_BASE + 0x200)
197197

198+
#define SUNXI_SOC_VER_REG (SUNXI_SYSCTRL_BASE + 0x24)
199+
#define SUNXI_SOC_VER_MASK (0x7)
200+
201+
#define SID_RES0_1_BASE (SUNXI_SID_BASE + 0x240)
202+
#define RESCAL_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x160)
203+
204+
#define INT_DSI_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x170)
205+
#define INT_CSI_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x174)
206+
#define INT_USB_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x178)
207+
208+
#define INT_EDP_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x180)
209+
#define INT_HS_COMBO_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x184)
210+
#define INT_DDR_RES_CTRL_REG (SUNXI_SYSCTRL_BASE + 0x188)
211+
198212
#endif// __SUN65IW1_REG_NCAT_H__

‎src/drivers/chips/sun252iw1/sys-dram.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919

2020
extern int init_DRAM(int type, void *buff);
2121

22-
static uint64_t dram_size;
22+
static uint32_t dram_size;
2323

2424
void __usdelay(unsigned long us) {
2525
udelay(us);

‎src/drivers/chips/sun55iw3/sys-dram.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818

1919
extern int init_DRAM(int type, void *buff);
2020

21-
static uint64_t dram_size;
21+
static uint32_t dram_size;
2222

2323
int set_ddr_voltage(unsigned int vol_val) {
2424
/* ddr voltage already set in main */

‎src/drivers/chips/sun65iw1/sys-dram.c‎

Lines changed: 76 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,18 +18,88 @@
1818
#include <sys-rtc.h>
1919
#include <pmu/axp.h>
2020

21+
#include <pmu/reg/reg-axp2202.h>
22+
2123
extern sunxi_i2c_t i2c_pmu;
2224

23-
void sunxi_smc_en_with_glitch_workaround(void) {
24-
return;
25+
static uint32_t AXP2202_RUNTIME_ADDR = 0x0;
26+
static uint32_t dram_size;
27+
28+
extern int init_DRAM(int type, void *buff);
29+
30+
int set_ddr_voltage(uint32_t vol_val) {
31+
printk_debug("Setting DDR voltage to %u mV for axp323 dcdc3\n", vol_val);
32+
pmu_axp1530_set_vol(&i2c_pmu, "dcdc3", vol_val, 1);
33+
return 0;
34+
}
35+
36+
void get_vdd_sys_pmu_id(void) {
37+
uint8_t axp_val;
38+
/* Try to probe AXP717B */
39+
if (sunxi_i2c_read(&i2c_pmu, AXP2202_B_RUNTIME_ADDR, AXP2202_CHIP_ID_EXT, &axp_val)) {
40+
/* AXP717B probe fail, Try to probe AXP717C */
41+
if (sunxi_i2c_read(&i2c_pmu, AXP2202_C_RUNTIME_ADDR, AXP2202_CHIP_ID_EXT, &axp_val)) {
42+
/* AXP717C probe fail */
43+
printk_warning("PMU: AXP2202 PMU Read error\n");
44+
return;
45+
} else {
46+
AXP2202_RUNTIME_ADDR = AXP2202_C_RUNTIME_ADDR;
47+
}
48+
} else {
49+
AXP2202_RUNTIME_ADDR = AXP2202_B_RUNTIME_ADDR;
50+
}
2551
}
2652

27-
int set_ddr_voltage_ext(char *name, int set_vol, int on) {
28-
printk_debug("PMU: %s set vol %d, onoff %d\n", name, set_vol, on);
29-
pmu_axp8191_set_vol(&i2c_pmu, name, set_vol, on);
53+
int set_vdd_sys_reg(int set_vol, int onoff) {
54+
uint8_t reg_value;
55+
56+
/* read cfg value */
57+
if (sunxi_i2c_read(&i2c_pmu, AXP2202_RUNTIME_ADDR, AXP2202_DC2OUT_VOL, &reg_value))
58+
return -1;
59+
60+
/* set voltage */
61+
reg_value &= ~0x7f;
62+
set_vol &= 0x7f;
63+
reg_value |= set_vol;
64+
sunxi_i2c_write(&i2c_pmu, AXP2202_RUNTIME_ADDR, AXP2202_DC2OUT_VOL, reg_value);
65+
66+
/* set on/onff */
67+
if (sunxi_i2c_read(&i2c_pmu, AXP2202_RUNTIME_ADDR, AXP2202_OUTPUT_CTL0, &reg_value))
68+
return -1;
69+
70+
if (onoff == 0) {
71+
reg_value &= ~(1 << 1);
72+
} else {
73+
reg_value |= (1 << 1);
74+
}
75+
sunxi_i2c_write(&i2c_pmu, AXP2202_RUNTIME_ADDR, AXP2202_OUTPUT_CTL0, reg_value);
76+
77+
printk_debug("Setting VDD_SYS to %d mV, state: %s\n", pmu_axp2202_get_vol(&i2c_pmu, "dcdc2"), onoff ? "ON" : "OFF");
78+
3079
return 0;
3180
}
3281

82+
uint8_t get_vdd_sys_reg(void) {
83+
uint8_t reg_val = 0;
84+
85+
if (sunxi_i2c_read(&i2c_pmu, AXP2202_RUNTIME_ADDR, AXP2202_DC2OUT_VOL, &reg_val))
86+
return -1;
87+
88+
printk_debug("Getting VDD_SYS reg = 0x%x\n", reg_val);
89+
return reg_val;
90+
}
91+
92+
void __usdelay(unsigned long us) {
93+
udelay((uint32_t) us);
94+
}
95+
96+
97+
uint32_t sunxi_get_dram_size() {
98+
return dram_size;
99+
}
100+
33101
uint32_t sunxi_dram_init(void *para) {
34-
return 0;
102+
get_vdd_sys_pmu_id();
103+
dram_size = init_DRAM(0, para);
104+
return dram_size;
35105
}

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