[VTA] Performance optimize, remove unnecessary contigious memory use.#4246
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tmoreau89 merged 2 commits intoapache:masterfrom Nov 2, 2019
huajsj:master
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[VTA] Performance optimize, remove unnecessary contigious memory use.#4246tmoreau89 merged 2 commits intoapache:masterfrom huajsj:master
tmoreau89 merged 2 commits intoapache:masterfrom
huajsj:master
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Issue: Uop maintain a cache vector to copy uop data into contigious DRAM memory for FPGA/Simulator use, but this cache vector not get clear after FPGA/Simulator core run, in Resnet18 case, if we printf the cache size in UopQueue::ReadBarrier function, we can saw such cache size keep increase, this would cause no use data copy and unnecessary contigous DRAM memory malloc. Analysis: This issue caused by not clear cache_ vector when do uop_queue_.Reset(). Solution: Override BaseQueue Reset function in UopQueue and add cache_ clear logic.
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Hi @tmoreau89, could you help to review this patch? Regards |
tmoreau89
reviewed
Nov 1, 2019
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Thanks for the catch @huajsj; was the fix tested in sim and hardware? |
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Author
Hi @tmoreau89 , Thanks for the follow up, yes , the fix get tested in both sim and pynq FPGA and work fine. Regards |
zxy844288792
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Nov 13, 2019
…apache#4246) * [VTA] Performance optimize, remove unnecessary contigious memory use. Issue: Uop maintain a cache vector to copy uop data into contigious DRAM memory for FPGA/Simulator use, but this cache vector not get clear after FPGA/Simulator core run, in Resnet18 case, if we printf the cache size in UopQueue::ReadBarrier function, we can saw such cache size keep increase, this would cause no use data copy and unnecessary contigous DRAM memory malloc. Analysis: This issue caused by not clear cache_ vector when do uop_queue_.Reset(). Solution: Override BaseQueue Reset function in UopQueue and add cache_ clear logic. * address review comments, remove spacing.
tqchen
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Mar 29, 2020
…apache#4246) * [VTA] Performance optimize, remove unnecessary contigious memory use. Issue: Uop maintain a cache vector to copy uop data into contigious DRAM memory for FPGA/Simulator use, but this cache vector not get clear after FPGA/Simulator core run, in Resnet18 case, if we printf the cache size in UopQueue::ReadBarrier function, we can saw such cache size keep increase, this would cause no use data copy and unnecessary contigous DRAM memory malloc. Analysis: This issue caused by not clear cache_ vector when do uop_queue_.Reset(). Solution: Override BaseQueue Reset function in UopQueue and add cache_ clear logic. * address review comments, remove spacing.
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Issue:
Uop maintain a cache vector to copy uop data into contigious DRAM memory for
FPGA/Simulator use, but this cache vector not get clear after FPGA/Simulator
core run, in Resnet18 case, if we printf the cache size in UopQueue::ReadBarrier
function, we can saw such cache size keep increase, this would cause
no use data copy and unnecessary contigous DRAM memory malloc.
Analysis:
This issue caused by not clear cache_ vector when do
uop_queue_.Reset().
Solution:
Override BaseQueue Reset function in UopQueue and add cache_ clear
logic.