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Simplify nested if_then_else when constant is appearing in then_expr
1 parent a9fcac1 commit 4998a87

2 files changed

Lines changed: 25 additions & 2 deletions

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src/arith/ir_mutator_with_analyzer.cc

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -173,8 +173,9 @@ PrimExpr IRMutatorWithAnalyzer::VisitExpr_(const CallNode* op) {
173173
WithRecordIterPredicate(cond, [&] { true_value = this->VisitExpr(op->args[1]); });
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}
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{
176-
With<ConstraintContext> constraint(analyzer_, analyzer_->rewrite_simplify(Not(cond)));
177-
false_value = this->VisitExpr(op->args[2]);
176+
PrimExpr not_cond = Not(cond);
177+
With<ConstraintContext> constraint(analyzer_, not_cond);
178+
WithRecordIterPredicate(not_cond, [&] { false_value = this->VisitExpr(op->args[2]); });
178179
}
179180
if (is_zero(cond)) {
180181
return false_value;

tests/python/tir-transform/test_tir_transform_simplify.py

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1757,5 +1757,27 @@ def expected(a: T.handle):
17571757
A[T.int64(1)] = T.float32(0)
17581758

17591759

1760+
class TestNestedIfElimination(BaseBeforeAfter):
1761+
def before(a: T.Buffer((2, 8), "int32"), b: T.Buffer((2, 8), "int32")):
1762+
for i0, j0 in T.grid(2, 8):
1763+
with T.block("P"):
1764+
i1, j1 = T.axis.remap("SS", [i0, j0])
1765+
T.reads(a[i1, j1])
1766+
T.writes(b[i1, j1])
1767+
b[i1, j1] = T.if_then_else(
1768+
i1 == 1 and 6 <= j1,
1769+
0,
1770+
T.max(0, T.if_then_else(i1 == 1 and 6 <= j1, 0, a[i1, j1])),
1771+
)
1772+
1773+
def expected(a: T.Buffer((2, 8), "int32"), b: T.Buffer((2, 8), "int32")):
1774+
for i0, j0 in T.grid(2, 8):
1775+
with T.block("P"):
1776+
i1, j1 = T.axis.remap("SS", [i0, j0])
1777+
T.reads(a[i1, j1])
1778+
T.writes(b[i1, j1])
1779+
b[i1, j1] = T.if_then_else(i1 == 1 and 6 <= j1, 0, T.max(0, a[i1, j1]))
1780+
1781+
17601782
if __name__ == "__main__":
17611783
tvm.testing.main()

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