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vegaluisjosetmoreau89
vegaluisjose
authored and
tmoreau89
committed
remove tabs (#3603)
1 parent 9911044 commit 66f3bf8

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10 files changed

+85
-85
lines changed

10 files changed

+85
-85
lines changed

‎vta/hardware/chisel/src/main/scala/core/Compute.scala‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -64,9 +64,9 @@ class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
6464

6565
val inst_type = Cat(dec.io.isFinish,
6666
dec.io.isAlu,
67-
dec.io.isGemm,
68-
dec.io.isLoadAcc,
69-
dec.io.isLoadUop).asUInt
67+
dec.io.isGemm,
68+
dec.io.isLoadAcc,
69+
dec.io.isLoadUop).asUInt
7070

7171
val sprev = inst_q.io.deq.valid & Mux(dec.io.pop_prev, s(0).io.sready, true.B)
7272
val snext = inst_q.io.deq.valid & Mux(dec.io.pop_next, s(1).io.sready, true.B)
@@ -87,11 +87,11 @@ class Compute(debug: Boolean = false)(implicit p: Parameters) extends Module {
8787
switch (state) {
8888
is (sIdle) {
8989
when (start) {
90-
when (dec.io.isSync) {
90+
when (dec.io.isSync) {
9191
state := sSync
92-
} .elsewhen (inst_type.orR) {
92+
} .elsewhen (inst_type.orR) {
9393
state := sExe
94-
}
94+
}
9595
}
9696
}
9797
is (sSync) {

‎vta/hardware/chisel/src/main/scala/core/Fetch.scala‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -77,15 +77,15 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
7777
is (sIdle) {
7878
when (pulse) {
7979
state := sReadCmd
80-
when (xsize < xmax) {
80+
when (xsize < xmax) {
8181
rlen := xsize
82-
ilen := xsize >> 1.U
82+
ilen := xsize >> 1.U
8383
xrem := 0.U
84-
} .otherwise {
84+
} .otherwise {
8585
rlen := xmax - 1.U
86-
ilen := (xmax >> 1.U) - 1.U
86+
ilen := (xmax >> 1.U) - 1.U
8787
xrem := xsize - xmax
88-
}
88+
}
8989
}
9090
}
9191
is (sReadCmd) {
@@ -104,7 +104,7 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
104104
state := sDrain
105105
} .otherwise {
106106
state := sReadLSB
107-
}
107+
}
108108
}
109109
}
110110
is (sDrain) {
@@ -114,12 +114,12 @@ class Fetch(debug: Boolean = false)(implicit p: Parameters) extends Module {
114114
} .elsewhen (xrem < xmax) {
115115
state := sReadCmd
116116
rlen := xrem
117-
ilen := xrem >> 1.U
117+
ilen := xrem >> 1.U
118118
xrem := 0.U
119119
} .otherwise {
120120
state := sReadCmd
121121
rlen := xmax - 1.U
122-
ilen := (xmax >> 1.U) - 1.U
122+
ilen := (xmax >> 1.U) - 1.U
123123
xrem := xrem - xmax
124124
}
125125
}

‎vta/hardware/chisel/src/main/scala/core/Load.scala‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -65,9 +65,9 @@ class Load(debug: Boolean = false)(implicit p: Parameters) extends Module {
6565
when (start) {
6666
when (dec.io.isSync) {
6767
state := sSync
68-
} .elsewhen (dec.io.isInput || dec.io.isWeight) {
68+
} .elsewhen (dec.io.isInput || dec.io.isWeight) {
6969
state := sExe
70-
}
70+
}
7171
}
7272
}
7373
is (sSync) {
@@ -121,10 +121,10 @@ class Load(debug: Boolean = false)(implicit p: Parameters) extends Module {
121121
when (state === sExe) {
122122
when (done) {
123123
when (dec.io.isInput) {
124-
printf("[Load] done input\n")
125-
} .elsewhen (dec.io.isWeight) {
126-
printf("[Load] done weight\n")
127-
}
124+
printf("[Load] done input\n")
125+
} .elsewhen (dec.io.isWeight) {
126+
printf("[Load] done weight\n")
127+
}
128128
}
129129
}
130130
}

‎vta/hardware/chisel/src/main/scala/core/LoadUop.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -91,13 +91,13 @@ class LoadUop(debug: Boolean = false)(implicit p: Parameters) extends Module {
9191
is (sIdle) {
9292
when (io.start) {
9393
state := sReadCmd
94-
when (xsize < xmax) {
94+
when (xsize < xmax) {
9595
xlen := xsize
9696
xrem := 0.U
97-
} .otherwise {
97+
} .otherwise {
9898
xlen := xmax - 1.U
9999
xrem := xsize - xmax
100-
}
100+
}
101101
}
102102
}
103103
is (sReadCmd) {

‎vta/hardware/chisel/src/main/scala/core/Store.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,9 +60,9 @@ class Store(debug: Boolean = false)(implicit p: Parameters) extends Module {
6060
when (start) {
6161
when (dec.io.isSync) {
6262
state := sSync
63-
} .elsewhen (dec.io.isStore) {
63+
} .elsewhen (dec.io.isStore) {
6464
state := sExe
65-
}
65+
}
6666
}
6767
}
6868
is (sSync) {
@@ -107,7 +107,7 @@ class Store(debug: Boolean = false)(implicit p: Parameters) extends Module {
107107
}
108108
when (state === sExe) {
109109
when (done) {
110-
printf("[Store] done\n")
110+
printf("[Store] done\n")
111111
}
112112
}
113113
}

‎vta/hardware/chisel/src/main/scala/core/TensorAlu.scala‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ class Alu(implicit p: Parameters) extends Module {
4343
Mux(io.a < io.b, io.b, io.a),
4444
io.a + io.b,
4545
io.a >> n,
46-
io.a << m)
46+
io.a << m)
4747

4848
val opmux = Seq.tabulate(ALU_OP_NUM)(i => ALU_OP(i) -> fop(i))
4949
io.y := MuxLookup(io.opcode, io.a, opmux)
@@ -157,8 +157,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
157157
is (sExe) {
158158
when (alu.io.out.data.valid) {
159159
when ((cnt_o === dec.lp_0 - 1.U) &&
160-
(cnt_i === dec.lp_1 - 1.U) &&
161-
(uop_idx === uop_end - 1.U)) {
160+
(cnt_i === dec.lp_1 - 1.U) &&
161+
(uop_idx === uop_end - 1.U)) {
162162
state := sIdle
163163
} .otherwise {
164164
state := sReadUop
@@ -169,8 +169,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
169169

170170
when (state === sIdle ||
171171
(state === sExe &&
172-
alu.io.out.data.valid &&
173-
uop_idx === uop_end - 1.U)) {
172+
alu.io.out.data.valid &&
173+
uop_idx === uop_end - 1.U)) {
174174
uop_idx := dec.uop_begin
175175
} .elsewhen (state === sExe && alu.io.out.data.valid) {
176176
uop_idx := uop_idx + 1.U
@@ -183,7 +183,7 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
183183
} .elsewhen (state === sExe &&
184184
alu.io.out.data.valid &&
185185
uop_idx === uop_end - 1.U &&
186-
cnt_i === dec.lp_1 - 1.U) {
186+
cnt_i === dec.lp_1 - 1.U) {
187187
cnt_o := cnt_o + 1.U
188188
dst_o := dst_o + dec.dst_0
189189
src_o := src_o + dec.src_0
@@ -199,7 +199,7 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
199199
src_i := src_o
200200
} .elsewhen (state === sExe &&
201201
alu.io.out.data.valid &&
202-
uop_idx === uop_end - 1.U) {
202+
uop_idx === uop_end - 1.U) {
203203
cnt_i := cnt_i + 1.U
204204
dst_i := dst_i + dec.dst_1
205205
src_i := src_i + dec.src_1

‎vta/hardware/chisel/src/main/scala/core/TensorGemm.scala‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -180,10 +180,10 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
180180
val done = inflight === 0.U &
181181
((state === sExe &
182182
cnt_o === dec.lp_0 - 1.U &
183-
cnt_i === dec.lp_1 - 1.U &
184-
uop_idx === uop_end - 1.U &
185-
inflight === 0.U) |
186-
state === sWait)
183+
cnt_i === dec.lp_1 - 1.U &
184+
uop_idx === uop_end - 1.U &
185+
inflight === 0.U) |
186+
state === sWait)
187187

188188
switch (state) {
189189
is (sIdle) {
@@ -204,11 +204,11 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
204204
when ((cnt_o === dec.lp_0 - 1.U) &&
205205
(cnt_i === dec.lp_1 - 1.U) &&
206206
(uop_idx === uop_end - 1.U)) {
207-
when (inflight =/= 0.U) {
207+
when (inflight =/= 0.U) {
208208
state := sWait
209-
} .otherwise {
209+
} .otherwise {
210210
state := sIdle
211-
}
211+
}
212212
} .otherwise {
213213
state := sReadUop
214214
}
@@ -232,7 +232,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
232232

233233
when (state === sIdle ||
234234
(state === sExe &&
235-
uop_idx === uop_end - 1.U)) {
235+
uop_idx === uop_end - 1.U)) {
236236
uop_idx := dec.uop_begin
237237
} .elsewhen (state === sExe) {
238238
uop_idx := uop_idx + 1.U
@@ -244,8 +244,8 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
244244
inp_o := 0.U
245245
wgt_o := 0.U
246246
} .elsewhen (state === sExe &&
247-
uop_idx === uop_end - 1.U &&
248-
cnt_i === dec.lp_1 - 1.U) {
247+
uop_idx === uop_end - 1.U &&
248+
cnt_i === dec.lp_1 - 1.U) {
249249
cnt_o := cnt_o + 1.U
250250
acc_o := acc_o + dec.acc_0
251251
inp_o := inp_o + dec.inp_0
@@ -263,7 +263,7 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends Module
263263
inp_i := inp_o
264264
wgt_i := wgt_o
265265
} .elsewhen (state === sExe &&
266-
uop_idx === uop_end - 1.U) {
266+
uop_idx === uop_end - 1.U) {
267267
cnt_i := cnt_i + 1.U
268268
acc_i := acc_i + dec.acc_1
269269
inp_i := inp_i + dec.inp_1

‎vta/hardware/chisel/src/main/scala/core/TensorLoad.scala‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -67,20 +67,20 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
6767
when (io.start) {
6868
when (dec.ypad_0 =/= 0.U) {
6969
state := sYPad0
70-
} .elsewhen (dec.xpad_0 =/= 0.U) {
70+
} .elsewhen (dec.xpad_0 =/= 0.U) {
7171
state := sXPad0
72-
} .otherwise {
72+
} .otherwise {
7373
state := sReadCmd
74-
}
74+
}
7575
}
7676
}
7777
is (sYPad0) {
7878
when (yPadCtrl0.io.done) {
7979
when (dec.xpad_0 =/= 0.U) {
8080
state := sXPad0
81-
} .otherwise {
81+
} .otherwise {
8282
state := sReadCmd
83-
}
83+
}
8484
}
8585
}
8686
is (sXPad0) {
@@ -96,22 +96,22 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
9696
is (sReadData) {
9797
when (io.vme_rd.data.valid) {
9898
when (dataCtrl.io.done) {
99-
when (dec.xpad_1 =/= 0.U) {
100-
state := sXPad1
101-
} .elsewhen (dec.ypad_1 =/= 0.U) {
102-
state := sYPad1
103-
} .otherwise {
104-
state := sIdle
105-
}
106-
} .elsewhen (dataCtrl.io.stride || dataCtrl.io.split) {
10799
when (dec.xpad_1 =/= 0.U) {
108-
state := sXPad1
109-
} .elsewhen (dec.xpad_0 =/= 0.U) {
100+
state := sXPad1
101+
} .elsewhen (dec.ypad_1 =/= 0.U) {
102+
state := sYPad1
103+
} .otherwise {
104+
state := sIdle
105+
}
106+
} .elsewhen (dataCtrl.io.stride || dataCtrl.io.split) {
107+
when (dec.xpad_1 =/= 0.U) {
108+
state := sXPad1
109+
} .elsewhen (dec.xpad_0 =/= 0.U) {
110110
state := sXPad0
111-
} .otherwise {
111+
} .otherwise {
112112
state := sReadCmd
113-
}
114-
}
113+
}
114+
}
115115
}
116116
}
117117
is (sXPad1) {
@@ -161,9 +161,9 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
161161

162162
xPadCtrl0.io.start := dec.xpad_0 =/= 0.U &
163163
((state === sIdle & io.start) |
164-
(state === sYPad0 & yPadCtrl0.io.done) |
164+
(state === sYPad0 & yPadCtrl0.io.done) |
165165
(io.vme_rd.data.fire() & ~dataCtrlDone & (dataCtrl.io.stride | dataCtrl.io.split) & dec.xpad_1 === 0.U) |
166-
(state === sXPad1 & xPadCtrl1.io.done & ~dataCtrlDone))
166+
(state === sXPad1 & xPadCtrl1.io.done & ~dataCtrlDone))
167167

168168
xPadCtrl1.io.start := dec.xpad_1 =/= 0.U & io.vme_rd.data.fire() &
169169
((dataCtrl.io.done) |
@@ -184,8 +184,8 @@ class TensorLoad(tensorType: String = "none", debug: Boolean = false)
184184
// write-to-sram
185185
val isZeroPad = state === sYPad0 |
186186
state === sXPad0 |
187-
state === sXPad1 |
188-
state === sYPad1
187+
state === sXPad1 |
188+
state === sYPad1
189189

190190
when (state === sIdle || state === sReadCmd || tag === (tp.numMemBlock - 1).U) {
191191
tag := 0.U

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