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aarkegzYanLien
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YanLien
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Update axerrno and page_table*, add comments, bump to 0.3.0 due to incompatible deps (#34)
* update axerrno to 0.2 * some small format fixes * update page_table_entry and page_table_multiarch dependencies to version 0.6 in Cargo.toml * chore: bump version to 0.3.0 in Cargo.toml * test: add multi-frame allocation support and fix warning * feat: update page_table_multiarch to 0.6 * fix: page table operations, to adapt `page_table*` 0.6 --------- Co-authored-by: YanLien <YJQ980314@outlook.com>
1 parent fd3f08b commit 1d16ab8

9 files changed

Lines changed: 75 additions & 83 deletions

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‎Cargo.toml‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ keywords = ["hypervisor", "address-space"]
1111
license = "Apache-2.0"
1212
name = "axaddrspace"
1313
repository = "https://github.com/arceos-hypervisor/axaddrspace"
14-
version = "0.2.0"
14+
version = "0.3.0"
1515

1616
[features]
1717
arm-el2 = ["page_table_entry/arm-el2"]
@@ -26,11 +26,11 @@ log = "0.4"
2626
numeric-enum-macro = "0.2"
2727

2828
# Operating system independent modules provided by ArceOS.
29-
axerrno = "0.1.0"
29+
axerrno = "0.2.0"
3030
memory_addr = "0.4"
3131
memory_set = "0.4"
32-
page_table_entry = "0.5"
33-
page_table_multiarch = "0.5"
32+
page_table_entry = "0.6"
33+
page_table_multiarch = "0.6"
3434

3535
[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
3636
x86 = "0.52"
@@ -40,4 +40,3 @@ lazy_static = "1.5"
4040
spin = "0.10"
4141
assert_matches = "1.5.0"
4242
axin = "0.1.0"
43-

‎src/address_space/backend/alloc.rs‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,6 @@ impl<H: PagingHandler> Backend<H> {
6161
size,
6262
MappingFlags::empty(),
6363
false,
64-
false,
6564
)
6665
.is_ok()
6766
}
@@ -76,7 +75,7 @@ impl<H: PagingHandler> Backend<H> {
7675
) -> bool {
7776
debug!("unmap_alloc: [{:#x}, {:#x})", start, start + size);
7877
for addr in PageIter4K::new(start, start + size).unwrap() {
79-
if let Ok((frame, page_size)) = pt.unmap(addr) {
78+
if let Ok((frame, _, page_size)) = pt.unmap(addr) {
8079
// Deallocate the physical frame if there is a mapping in the
8180
// page table.
8281
if page_size.is_huge() {

‎src/address_space/backend/linear.rs‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,6 @@ impl<H: PagingHandler> Backend<H> {
4747
size,
4848
flags,
4949
true,
50-
true,
5150
)
5251
.is_ok()
5352
}
@@ -60,6 +59,6 @@ impl<H: PagingHandler> Backend<H> {
6059
_pa_va_offset: usize,
6160
) -> bool {
6261
debug!("unmap_linear: [{:#x}, {:#x})", start, start + size);
63-
pt.unmap_region(start, size, true).is_ok()
62+
pt.unmap_region(start, size).is_ok()
6463
}
6564
}

‎src/address_space/backend/mod.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ impl<H: PagingHandler> MappingBackend for Backend<H> {
9898
new_flags: MappingFlags,
9999
page_table: &mut PageTable<H>,
100100
) -> bool {
101-
page_table.protect_region(start, size, new_flags, true)
101+
page_table.protect_region(start, size, new_flags)
102102
}
103103
}
104104

‎src/address_space/mod.rs‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
use alloc::vec::Vec;
1616
use core::fmt;
1717

18-
use axerrno::ax_err;
18+
use axerrno::{AxResult, ax_err};
1919
use memory_addr::{MemoryAddr, PhysAddr, is_aligned_4k};
2020
use memory_set::{MemoryArea, MemorySet};
2121
use page_table_multiarch::PagingHandler;
@@ -25,7 +25,6 @@ use crate::{GuestPhysAddr, GuestPhysAddrRange, mapping_err_to_ax_err};
2525

2626
mod backend;
2727

28-
pub use axerrno::{AxError, AxResult};
2928
pub use backend::Backend;
3029
pub use page_table_entry::MappingFlags;
3130

‎src/lib.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ pub use hal::AxMmHal;
3737

3838
pub use memory_accessor::GuestMemoryAccessor;
3939

40+
use axerrno::AxError;
4041
use memory_set::MappingError;
4142

4243
/// Information about nested page faults.

‎src/npt/arch/x86_64.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -190,6 +190,7 @@ impl PagingMetaData for ExtendedPageTableMetadata {
190190

191191
// Under the x86 architecture, the flush_tlb operation will invoke the ring0 instruction,
192192
// causing the test to trigger a SIGSEGV exception.
193+
#[allow(unused_variables)]
193194
fn flush_tlb(vaddr: Option<GuestPhysAddr>) {
194195
#[cfg(not(test))]
195196
if let Some(vaddr) = vaddr {

‎src/npt/mod.rs‎

Lines changed: 44 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -16,20 +16,21 @@ use axerrno::{ax_err, ax_err_type};
1616
use memory_addr::PhysAddr;
1717
use memory_set::MappingError;
1818
use page_table_entry::MappingFlags;
19-
use page_table_multiarch::PagingHandler;
19+
use page_table_multiarch::{PageSize, PagingHandler};
2020

2121
use crate::GuestPhysAddr;
2222

2323
cfg_if::cfg_if! {
2424
if #[cfg(target_arch = "x86_64")] {
2525
pub type NestedPageTableL4<H> = arch::ExtendedPageTable<H>;
26-
2726
} else if #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] {
27+
/// RISC-V Level 3 nested page table (Sv39, x4 not supported)
2828
pub type NestedPageTableL3<H> = page_table_multiarch::PageTable64<arch::Sv39MetaData<GuestPhysAddr>, arch::Rv64PTE, H>;
29-
pub type NestedPageTableL4<H> = page_table_multiarch::PageTable64<arch::Sv48MetaData<GuestPhysAddr>, arch::Rv64PTE, H>;
3029

30+
/// RISC-V Level 4 nested page table (Sv48, x4 not supported)
31+
pub type NestedPageTableL4<H> = page_table_multiarch::PageTable64<arch::Sv48MetaData<GuestPhysAddr>, arch::Rv64PTE, H>;
3132
} else if #[cfg(target_arch = "aarch64")] {
32-
/// AArch64 Level 3 nested page table type alias.
33+
/// AArch64 Level 3 nested page table type alias.
3334
pub type NestedPageTableL3<H> = page_table_multiarch::PageTable64<arch::A64HVPagingMetaDataL3, arch::A64PTEHV, H>;
3435

3536
/// AArch64 Level 4 nested page table type alias.
@@ -51,8 +52,6 @@ impl<H: PagingHandler> NestedPageTable<H> {
5152
3 => {
5253
#[cfg(not(target_arch = "x86_64"))]
5354
{
54-
use axerrno::ax_err_type;
55-
5655
let res = NestedPageTableL3::try_new().map_err(|_| ax_err_type!(NoMemory))?;
5756
Ok(NestedPageTable::L3(res))
5857
}
@@ -69,7 +68,7 @@ impl<H: PagingHandler> NestedPageTable<H> {
6968
}
7069
}
7170

72-
pub fn root_paddr(&self) -> memory_addr::PhysAddr {
71+
pub const fn root_paddr(&self) -> PhysAddr {
7372
match self {
7473
#[cfg(not(target_arch = "x86_64"))]
7574
NestedPageTable::L3(pt) => pt.root_paddr(),
@@ -81,22 +80,20 @@ impl<H: PagingHandler> NestedPageTable<H> {
8180
pub fn map(
8281
&mut self,
8382
vaddr: crate::GuestPhysAddr,
84-
paddr: memory_addr::PhysAddr,
85-
size: page_table_multiarch::PageSize,
83+
paddr: PhysAddr,
84+
size: PageSize,
8685
flags: page_table_entry::MappingFlags,
8786
) -> memory_set::MappingResult {
8887
match self {
8988
#[cfg(not(target_arch = "x86_64"))]
90-
NestedPageTable::L3(pt) => {
91-
pt.map(vaddr, paddr, size, flags)
92-
.map_err(|_| MappingError::BadState)?
93-
.flush();
94-
}
95-
NestedPageTable::L4(pt) => {
96-
pt.map(vaddr, paddr, size, flags)
97-
.map_err(|_| MappingError::BadState)?
98-
.flush();
99-
}
89+
NestedPageTable::L3(pt) => pt
90+
.cursor()
91+
.map(vaddr, paddr, size, flags)
92+
.map_err(|_| MappingError::BadState)?,
93+
NestedPageTable::L4(pt) => pt
94+
.cursor()
95+
.map(vaddr, paddr, size, flags)
96+
.map_err(|_| MappingError::BadState)?,
10097
}
10198
Ok(())
10299
}
@@ -105,19 +102,11 @@ impl<H: PagingHandler> NestedPageTable<H> {
105102
pub fn unmap(
106103
&mut self,
107104
vaddr: GuestPhysAddr,
108-
) -> memory_set::MappingResult<(memory_addr::PhysAddr, page_table_multiarch::PageSize)> {
105+
) -> memory_set::MappingResult<(PhysAddr, MappingFlags, PageSize)> {
109106
match self {
110107
#[cfg(not(target_arch = "x86_64"))]
111-
NestedPageTable::L3(pt) => {
112-
let (addr, size, f) = pt.unmap(vaddr).map_err(|_| MappingError::BadState)?;
113-
f.flush();
114-
Ok((addr, size))
115-
}
116-
NestedPageTable::L4(pt) => {
117-
let (addr, size, f) = pt.unmap(vaddr).map_err(|_| MappingError::BadState)?;
118-
f.flush();
119-
Ok((addr, size))
120-
}
108+
NestedPageTable::L3(pt) => pt.cursor().unmap(vaddr).map_err(|_| MappingError::BadState),
109+
NestedPageTable::L4(pt) => pt.cursor().unmap(vaddr).map_err(|_| MappingError::BadState),
121110
}
122111
}
123112

@@ -129,52 +118,42 @@ impl<H: PagingHandler> NestedPageTable<H> {
129118
size: usize,
130119
flags: MappingFlags,
131120
allow_huge: bool,
132-
flush_tlb_by_page: bool,
133121
) -> memory_set::MappingResult {
134122
match self {
135123
#[cfg(not(target_arch = "x86_64"))]
136-
NestedPageTable::L3(pt) => {
137-
pt.map_region(vaddr, get_paddr, size, flags, allow_huge, flush_tlb_by_page)
138-
.map_err(|_| MappingError::BadState)?
139-
.flush_all();
140-
}
141-
NestedPageTable::L4(pt) => {
142-
pt.map_region(vaddr, get_paddr, size, flags, allow_huge, flush_tlb_by_page)
143-
.map_err(|_| MappingError::BadState)?
144-
.flush_all();
145-
}
124+
NestedPageTable::L3(pt) => pt
125+
.cursor()
126+
.map_region(vaddr, get_paddr, size, flags, allow_huge)
127+
.map_err(|_| MappingError::BadState)?,
128+
NestedPageTable::L4(pt) => pt
129+
.cursor()
130+
.map_region(vaddr, get_paddr, size, flags, allow_huge)
131+
.map_err(|_| MappingError::BadState)?,
146132
}
147133
Ok(())
148134
}
149135

150136
/// Unmaps a region.
151-
pub fn unmap_region(
152-
&mut self,
153-
start: GuestPhysAddr,
154-
size: usize,
155-
flush: bool,
156-
) -> memory_set::MappingResult {
137+
pub fn unmap_region(&mut self, start: GuestPhysAddr, size: usize) -> memory_set::MappingResult {
157138
match self {
158139
#[cfg(not(target_arch = "x86_64"))]
159-
NestedPageTable::L3(pt) => {
160-
pt.unmap_region(start, size, flush)
161-
.map_err(|_| MappingError::BadState)?
162-
.ignore();
163-
}
164-
NestedPageTable::L4(pt) => {
165-
pt.unmap_region(start, size, flush)
166-
.map_err(|_| MappingError::BadState)?
167-
.ignore();
168-
}
140+
NestedPageTable::L3(pt) => pt
141+
.cursor()
142+
.unmap_region(start, size)
143+
.map_err(|_| MappingError::BadState)?,
144+
NestedPageTable::L4(pt) => pt
145+
.cursor()
146+
.unmap_region(start, size)
147+
.map_err(|_| MappingError::BadState)?,
169148
}
170149
Ok(())
171150
}
172151

173152
pub fn remap(&mut self, start: GuestPhysAddr, paddr: PhysAddr, flags: MappingFlags) -> bool {
174153
match self {
175154
#[cfg(not(target_arch = "x86_64"))]
176-
NestedPageTable::L3(pt) => pt.remap(start, paddr, flags).is_ok(),
177-
NestedPageTable::L4(pt) => pt.remap(start, paddr, flags).is_ok(),
155+
NestedPageTable::L3(pt) => pt.cursor().remap(start, paddr, flags).is_ok(),
156+
NestedPageTable::L4(pt) => pt.cursor().remap(start, paddr, flags).is_ok(),
178157
}
179158
}
180159

@@ -184,19 +163,16 @@ impl<H: PagingHandler> NestedPageTable<H> {
184163
start: GuestPhysAddr,
185164
size: usize,
186165
new_flags: page_table_entry::MappingFlags,
187-
flush: bool,
188166
) -> bool {
189167
match self {
190168
#[cfg(not(target_arch = "x86_64"))]
191169
NestedPageTable::L3(pt) => pt
192-
.protect_region(start, size, new_flags, flush) // If the TLB is refreshed immediately every time, there might be performance issues.
193-
// The TLB refresh is managed uniformly at a higher level.
194-
.map(|tlb| tlb.ignore())
170+
.cursor()
171+
.protect_region(start, size, new_flags) // If the TLB is refreshed immediately every time, there might be performance issues.
195172
.is_ok(),
196173
NestedPageTable::L4(pt) => pt
197-
.protect_region(start, size, new_flags, flush) // If the TLB is refreshed immediately every time, there might be performance issues.
198-
// The TLB refresh is managed uniformly at a higher level.
199-
.map(|tlb| tlb.ignore())
174+
.cursor()
175+
.protect_region(start, size, new_flags) // If the TLB is refreshed immediately every time, there might be performance issues.
200176
.is_ok(),
201177
}
202178
}
@@ -205,11 +181,8 @@ impl<H: PagingHandler> NestedPageTable<H> {
205181
pub fn query(
206182
&self,
207183
vaddr: crate::GuestPhysAddr,
208-
) -> page_table_multiarch::PagingResult<(
209-
memory_addr::PhysAddr,
210-
page_table_entry::MappingFlags,
211-
page_table_multiarch::PageSize,
212-
)> {
184+
) -> page_table_multiarch::PagingResult<(PhysAddr, page_table_entry::MappingFlags, PageSize)>
185+
{
213186
match self {
214187
#[cfg(not(target_arch = "x86_64"))]
215188
NestedPageTable::L3(pt) => pt.query(vaddr),

‎src/test_utils/mod.rs‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,10 +90,31 @@ impl PagingHandler for MockHal {
9090
Self::mock_alloc_frame()
9191
}
9292

93+
fn alloc_frames(count: usize, _align: usize) -> Option<PhysAddr> {
94+
if count == 0 {
95+
return Some(PhysAddr::from(0));
96+
}
97+
// For simplicity, just allocate frames sequentially
98+
let first = Self::mock_alloc_frame()?;
99+
for _ in 1..count {
100+
if Self::mock_alloc_frame().is_none() {
101+
return None;
102+
}
103+
}
104+
Some(first)
105+
}
106+
93107
fn dealloc_frame(_paddr: PhysAddr) {
94108
Self::mock_dealloc_frame(_paddr)
95109
}
96110

111+
fn dealloc_frames(paddr: PhysAddr, count: usize) {
112+
for i in 0..count {
113+
let offset = i * PAGE_SIZE;
114+
Self::mock_dealloc_frame(PhysAddr::from(paddr.as_usize() + offset));
115+
}
116+
}
117+
97118
fn phys_to_virt(paddr: PhysAddr) -> VirtAddr {
98119
Self::mock_phys_to_virt(paddr)
99120
}

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