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feat: update page_table_multiarch to 0.6
1 parent 230a227 commit c584a75

4 files changed

Lines changed: 27 additions & 29 deletions

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Cargo.toml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ numeric-enum-macro = "0.2"
3030
axerrno = "0.1.0"
3131
memory_addr = "0.4"
3232
memory_set = "0.4"
33-
page_table_entry = "=0.5.7"
34-
page_table_multiarch = "=0.5.7"
33+
page_table_entry = "0.6"
34+
page_table_multiarch = "0.6"
3535

3636
[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
3737
x86 = "0.52"

src/address_space/backend/alloc.rs

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ impl<H: PagingHandler> Backend<H> {
3232
// allocate all possible physical frames for populated mapping.
3333
for addr in PageIter4K::new(start, start + size).unwrap() {
3434
if H::alloc_frame()
35-
.and_then(|frame| pt.map(addr, frame, PageSize::Size4K, flags).ok())
35+
.and_then(|frame| pt.cursor().map(addr, frame, PageSize::Size4K, flags).ok())
3636
.is_none()
3737
{
3838
return false;
@@ -41,15 +41,15 @@ impl<H: PagingHandler> Backend<H> {
4141
true
4242
} else {
4343
// Map to a empty entry for on-demand mapping.
44-
pt.map_region(
45-
start,
46-
|_va| PhysAddr::from(0),
47-
size,
48-
MappingFlags::empty(),
49-
false,
50-
false,
51-
)
52-
.is_ok()
44+
pt.cursor()
45+
.map_region(
46+
start,
47+
|_va| PhysAddr::from(0),
48+
size,
49+
MappingFlags::empty(),
50+
false,
51+
)
52+
.is_ok()
5353
}
5454
}
5555

@@ -62,7 +62,7 @@ impl<H: PagingHandler> Backend<H> {
6262
) -> bool {
6363
debug!("unmap_alloc: [{:#x}, {:#x})", start, start + size);
6464
for addr in PageIter4K::new(start, start + size).unwrap() {
65-
if let Ok((frame, page_size, _)) = pt.unmap(addr) {
65+
if let Ok((frame, _, page_size)) = pt.cursor().unmap(addr) {
6666
// Deallocate the physical frame if there is a mapping in the
6767
// page table.
6868
if page_size.is_huge() {
@@ -88,9 +88,9 @@ impl<H: PagingHandler> Backend<H> {
8888
} else {
8989
// Allocate a physical frame lazily and map it to the fault address.
9090
// `vaddr` does not need to be aligned. It will be automatically
91-
// aligned during `pt.remap` regardless of the page size.
91+
// aligned during `pt.cursor().remap` regardless of the page size.
9292
H::alloc_frame()
93-
.and_then(|frame| pt.remap(vaddr, frame, orig_flags).ok())
93+
.and_then(|frame| pt.cursor().remap(vaddr, frame, orig_flags).ok())
9494
.is_some()
9595
}
9696
}

src/address_space/backend/linear.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -27,15 +27,15 @@ impl<H: PagingHandler> Backend<H> {
2727
pa_start + size,
2828
flags
2929
);
30-
pt.map_region(
31-
start,
32-
|va| PhysAddr::from(va.as_usize() - pa_va_offset),
33-
size,
34-
flags,
35-
true,
36-
true,
37-
)
38-
.is_ok()
30+
pt.cursor()
31+
.map_region(
32+
start,
33+
|va| PhysAddr::from(va.as_usize() - pa_va_offset),
34+
size,
35+
flags,
36+
true,
37+
)
38+
.is_ok()
3939
}
4040

4141
pub(crate) fn unmap_linear(
@@ -46,6 +46,6 @@ impl<H: PagingHandler> Backend<H> {
4646
_pa_va_offset: usize,
4747
) -> bool {
4848
debug!("unmap_linear: [{:#x}, {:#x})", start, start + size);
49-
pt.unmap_region(start, size, true).is_ok()
49+
pt.cursor().unmap_region(start, size).is_ok()
5050
}
5151
}

src/address_space/backend/mod.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,10 +85,8 @@ impl<H: PagingHandler> MappingBackend for Backend<H> {
8585
page_table: &mut PageTable<H>,
8686
) -> bool {
8787
page_table
88-
.protect_region(start, size, new_flags, true)
89-
// If the TLB is refreshed immediately every time, there might be performance issues.
90-
// The TLB refresh is managed uniformly at a higher level.
91-
.map(|tlb| tlb.ignore())
88+
.cursor()
89+
.protect_region(start, size, new_flags)
9290
.is_ok()
9391
}
9492
}

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