pulley: Finish simd proposal implementation

This commit fills out the final and miscellaneous set of opcodes for
Pulley to have a complete implementation of the `simd` proposal for
WebAssembly. All spec tests are now enabled and the Pulley-specific
exceptions for `*.wast` tests are all gone.

Closes #9783

Author: alexcrichton

cranelift/codegen/src/isa/pulley_shared/lower.isle

@@ -985,6 +985,9 @@
 (rule 1 (lower (has_type $F64 (select c a b)))
   (pulley_fselect64 (emit_cond (lower_cond c)) a b))
 
+(rule 2 (lower (has_type (ty_vec128 _) (select c a b)))
+  (pulley_vselect (emit_cond (lower_cond c)) a b))
+
 ;; Helper to emit a conditional into a register itself.
 (decl emit_cond (Cond) XReg)
 (rule (emit_cond (Cond.If32 reg)) reg)
@@ -1157,6 +1160,18 @@
 (rule (lower (has_type $I64 (fcvt_to_sint_sat val @ (value_type $F64))))
   (pulley_x64_from_f64_s_sat val))
 
+(rule (lower (has_type $I32X4 (fcvt_to_sint_sat val @ (value_type $F32X4))))
+  (pulley_vi32x4_from_f32x4_s val))
+
+(rule (lower (has_type $I32X4 (fcvt_to_uint_sat val @ (value_type $F32X4))))
+  (pulley_vi32x4_from_f32x4_u val))
+
+(rule (lower (has_type $I64X2 (fcvt_to_sint_sat val @ (value_type $F64X2))))
+  (pulley_vi64x2_from_f64x2_s val))
+
+(rule (lower (has_type $I64X2 (fcvt_to_uint_sat val @ (value_type $F64X2))))
+  (pulley_vi64x2_from_f64x2_u val))
+
 ;;;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $F32 (fdemote val @ (value_type $F64))))
@@ -1373,12 +1388,17 @@
 
 (rule (lower (snarrow a @ (value_type $I16X8) b)) (pulley_vnarrow16x8_s a b))
 (rule (lower (snarrow a @ (value_type $I32X4) b)) (pulley_vnarrow32x4_s a b))
+(rule (lower (snarrow a @ (value_type $I64X2) b)) (pulley_vnarrow64x2_s a b))
 
 ;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (unarrow a @ (value_type $I16X8) b)) (pulley_vnarrow16x8_u a b))
 (rule (lower (unarrow a @ (value_type $I32X4) b)) (pulley_vnarrow32x4_u a b))
 
+;;;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (uunarrow a @ (value_type $I64X2) b)) (pulley_vunarrow64x2_u a b))
+
 ;;;; Rules for `fvpromote_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (fvpromote_low a @ (value_type $F32X4))) (pulley_vfpromotelow a))

cranelift/filetests/filetests/runtests/simd-arithmetic.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %sadd_sat_i8x16(i8x16, i8x16) -> i8x16 {

cranelift/filetests/filetests/runtests/simd-avg-round.clif

@@ -6,6 +6,10 @@ target x86_64 skylake
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %average_rounding_i8x16(i8x16, i8x16) -> i8x16 {
 block0(v0: i8x16, v1: i8x16):

cranelift/filetests/filetests/runtests/simd-band-splat.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %band_splat_const_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):

cranelift/filetests/filetests/runtests/simd-bitcast.clif

@@ -7,6 +7,10 @@ target s390x
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %bitcast_if32x4(i32x4) -> f32x4 {
 block0(v0: i32x4):

cranelift/filetests/filetests/runtests/simd-bitselect-to-vselect.clif

@@ -7,6 +7,10 @@ target x86_64 skylake
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %mask_from_icmp(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):

cranelift/filetests/filetests/runtests/simd-bitselect.clif

@@ -7,6 +7,10 @@ set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
 set enable_multi_ret_implicit_sret=false
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 set opt_level=speed
 target aarch64
@@ -16,6 +20,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %bitselect_i64x2(i64x2, i64x2, i64x2) -> i64x2 {
 block0(v0: i64x2, v1: i64x2, v2: i64x2):

cranelift/filetests/filetests/runtests/simd-bor-splat.clif

@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %bor_splat_const_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):

cranelift/filetests/filetests/runtests/simd-bxor-splat.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %bxor_splat_const_i8x16(i8x16) -> i8x16 {
 block0(v0: i8x16):

cranelift/filetests/filetests/runtests/simd-ceil.clif

@@ -9,6 +9,10 @@ target s390x
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %ceil_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):