Add ELF TLS support in new x64 backend.

This follows the implementation in the legacy x86 backend, including
hardcoded sequence that is compatible with what the linker expects. We
could potentially do better here, but it is likely not necessary.

Thanks to @bjorn3 for a bugfix to an earlier version of this.

Author: cfallin

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -1,5 +1,6 @@
 use crate::binemit::{Addend, Reloc};
 use crate::ir::immediates::{Ieee32, Ieee64};
+use crate::ir::LibCall;
 use crate::ir::TrapCode;
 use crate::isa::x64::inst::args::*;
 use crate::isa::x64::inst::*;
@@ -2937,6 +2938,27 @@ pub(crate) fn emit(
         Inst::EpiloguePlaceholder => {
             // Generate no code.
         }
+
+        Inst::ElfTlsGetAddr { ref symbol } => {
+            sink.put1(0x66);
+            sink.put1(0b01001000);
+            sink.put1(0x8d);
+            sink.put1(0x3d);
+            emit_reloc(sink, state, Reloc::ElfX86_64TlsGd, symbol, -4);
+            sink.put4(0);
+            sink.put1(0x66);
+            sink.put1(0x66);
+            sink.put1(0b01001000);
+            sink.put1(0xe8);
+            emit_reloc(
+                sink,
+                state,
+                Reloc::X86CallPLTRel4,
+                &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
+                -4,
+            );
+            sink.put4(0);
+        }
     }
 
     state.clear_post_insn();

cranelift/codegen/src/isa/x64/inst/emit_tests.rs

@@ -3779,6 +3779,17 @@ fn test_x64_emit() {
     let trap_code = TrapCode::UnreachableCodeReached;
     insns.push((Inst::Ud2 { trap_code }, "0F0B", "ud2 unreachable"));
 
+    insns.push((
+        Inst::ElfTlsGetAddr {
+            symbol: ExternalName::User {
+                namespace: 0,
+                index: 0,
+            },
+        },
+        "66488D3D00000000666648E800000000",
+        "elf_tls_get_addr User { namespace: 0, index: 0 }",
+    ));
+
     // ========================================================
     // Actually run the tests!
     let flags = settings::Flags::new(settings::builder());

cranelift/codegen/src/isa/x64/inst/mod.rs

@@ -471,6 +471,10 @@ pub enum Inst {
     /// reports its own `def`s/`use`s/`mod`s; this adds complexity (the instruction list is no
     /// longer flat) and requires knowledge about semantics and initial-value independence anyway.
     XmmUninitializedValue { dst: Writable<Reg> },
+
+    /// A call to the `ElfTlsGetAddr` libcall. Returns address
+    /// of TLS symbol in rax.
+    ElfTlsGetAddr { symbol: ExternalName },
 }
 
 pub(crate) fn low32_will_sign_extend_to_64(x: u64) -> bool {
@@ -529,7 +533,8 @@ impl Inst {
             | Inst::XmmCmpRmR { .. }
             | Inst::XmmLoadConst { .. }
             | Inst::XmmMinMaxSeq { .. }
-            | Inst::XmmUninitializedValue { .. } => None,
+            | Inst::XmmUninitializedValue { .. }
+            | Inst::ElfTlsGetAddr { .. } => None,
 
             // These use dynamic SSE opcodes.
             Inst::GprToXmm { op, .. }
@@ -1759,6 +1764,10 @@ impl PrettyPrint for Inst {
             Inst::Hlt => "hlt".into(),
 
             Inst::Ud2 { trap_code } => format!("ud2 {}", trap_code),
+
+            Inst::ElfTlsGetAddr { ref symbol } => {
+                format!("elf_tls_get_addr {:?}", symbol)
+            }
         }
     }
 }
@@ -2018,6 +2027,36 @@ fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
         | Inst::Fence { .. } => {
             // No registers are used.
         }
+
+        Inst::ElfTlsGetAddr { .. } => {
+            // All caller-saves are clobbered.
+            collector.add_def(Writable::from_reg(regs::rsi()));
+            collector.add_def(Writable::from_reg(regs::rdi()));
+            collector.add_def(Writable::from_reg(regs::rax()));
+            collector.add_def(Writable::from_reg(regs::rcx()));
+            collector.add_def(Writable::from_reg(regs::rdx()));
+            collector.add_def(Writable::from_reg(regs::r8()));
+            collector.add_def(Writable::from_reg(regs::r9()));
+            collector.add_def(Writable::from_reg(regs::r10()));
+            collector.add_def(Writable::from_reg(regs::r11()));
+
+            collector.add_def(Writable::from_reg(regs::xmm0()));
+            collector.add_def(Writable::from_reg(regs::xmm1()));
+            collector.add_def(Writable::from_reg(regs::xmm2()));
+            collector.add_def(Writable::from_reg(regs::xmm3()));
+            collector.add_def(Writable::from_reg(regs::xmm4()));
+            collector.add_def(Writable::from_reg(regs::xmm5()));
+            collector.add_def(Writable::from_reg(regs::xmm6()));
+            collector.add_def(Writable::from_reg(regs::xmm7()));
+            collector.add_def(Writable::from_reg(regs::xmm8()));
+            collector.add_def(Writable::from_reg(regs::xmm9()));
+            collector.add_def(Writable::from_reg(regs::xmm10()));
+            collector.add_def(Writable::from_reg(regs::xmm11()));
+            collector.add_def(Writable::from_reg(regs::xmm12()));
+            collector.add_def(Writable::from_reg(regs::xmm13()));
+            collector.add_def(Writable::from_reg(regs::xmm14()));
+            collector.add_def(Writable::from_reg(regs::xmm15()));
+        }
     }
 }
 
@@ -2393,6 +2432,7 @@ fn x64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
         | Inst::Ud2 { .. }
         | Inst::Hlt
         | Inst::AtomicRmwSeq { .. }
+        | Inst::ElfTlsGetAddr { .. }
         | Inst::Fence { .. } => {
             // Instruction doesn't explicitly mention any regs, so it can't have any virtual
             // regs that we'd need to remap.  Hence no action required.

cranelift/codegen/src/isa/x64/lower.rs

@@ -12,7 +12,7 @@ use crate::isa::{x64::X64Backend, CallConv};
 use crate::machinst::lower::*;
 use crate::machinst::*;
 use crate::result::CodegenResult;
-use crate::settings::Flags;
+use crate::settings::{Flags, TlsModel};
 use alloc::boxed::Box;
 use alloc::vec::Vec;
 use cranelift_codegen_shared::condcodes::CondCode;
@@ -4238,6 +4238,22 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             }
         }
 
+        Opcode::TlsValue => match flags.tls_model() {
+            TlsModel::ElfGd => {
+                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
+                let (name, _, _) = ctx.symbol_value(insn).unwrap();
+                let symbol = name.clone();
+                ctx.emit(Inst::ElfTlsGetAddr { symbol });
+                ctx.emit(Inst::gen_move(dst, regs::rax(), types::I64));
+            }
+            _ => {
+                todo!(
+                    "Unimplemented TLS model in x64 backend: {:?}",
+                    flags.tls_model()
+                );
+            }
+        },
+
         Opcode::IaddImm
         | Opcode::ImulImm
         | Opcode::UdivImm

cranelift/filetests/filetests/isa/x64/tls_elf.clif

@@ -0,0 +1,19 @@
+test compile
+set tls_model=elf_gd
+target x86_64
+feature "experimental_x64"
+
+function u0:0(i32) -> i64 {
+gv0 = symbol colocated tls u1:0
+
+block0(v0: i32):
+    v1 = global_value.i64 gv0
+    return v1
+}
+
+; check:  pushq   %rbp
+; nextln: movq    %rsp, %rbp
+; nextln: elf_tls_get_addr User { namespace: 1, index: 0 }
+; nextln: movq    %rbp, %rsp
+; nextln: popq    %rbp
+; nextln: ret