x86/cpufeatures: Add CSV3 CPU feature

hygon inclusion
category: feature
CVE: NA

---------------------------

Add CPU feature detection for Hygon 3rd CSV. This feature enhances
CSV2 by also isolating NPT and VMCB, making them in-accessible to
the hypervisor.

Signed-off-by: hanliyang <hanliyang@hygon.cn>

Author: hanliyang

arch/x86/include/asm/cpufeatures.h

@@ -465,6 +465,8 @@
 #define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* "" Virtual TSC_AUX */
 #define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
 #define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* AMD SEV-ES full debug state swap support */
+/* HYGON 3rd CSV */
+#define X86_FEATURE_CSV3		(19*32 + 30) /* HYGON 3rd CSV */
 
 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
 #define X86_FEATURE_NO_NESTED_DATA_BP	(20*32+ 0) /* "" No Nested Data Breakpoints */

arch/x86/kernel/cpu/hygon.c

@@ -300,6 +300,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
 clear_csv:
 	setup_clear_cpu_cap(X86_FEATURE_SEV);
 	setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
+	setup_clear_cpu_cap(X86_FEATURE_CSV3);
 }
 
 static void early_init_hygon(struct cpuinfo_x86 *c)