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IP Upgrade report for niosii_top
Fri Feb 16 22:11:32 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. IP Upgrade Summary
3. Successfully Upgraded IP Components
4. IP Upgrade Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2023 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------+
; IP Upgrade Summary ;
+------------------------------+------------------------------------------------+
; IP Components Upgrade Status ; Passed - Fri Feb 16 22:11:32 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; niosii_top ;
; Top-level Entity Name ; DE0_CV ;
; Family ; Cyclone V ;
+------------------------------+------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Successfully Upgraded IP Components ;
+-------------+----------------+---------+-------------------------------------+----------------------+-------------------------------------+---------+
; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ;
+-------------+----------------+---------+-------------------------------------+----------------------+-------------------------------------+---------+
; niosii_top ; Qsys ; 22.1 ; niosii_top/synthesis/niosii_top.qip ; niosii_top.qsys ; niosii_top/synthesis/niosii_top.qip ; ;
+-------------+----------------+---------+-------------------------------------+----------------------+-------------------------------------+---------+
+---------------------+
; IP Upgrade Messages ;
+---------------------+
Info (11902): Backing up file "niosii_top.qsys" to "niosii_top.BAK.qsys"
Info (11902): Backing up file "niosii_top/synthesis/niosii_top.v" to "niosii_top.BAK.v"
Info (11837): Started upgrading IP component Qsys with file "niosii_top.qsys"
Info: 2024.02.16.22:10:34 Info: Starting to upgrade the IP cores in the Platform Designer system
Info: 2024.02.16.22:10:34 Info: Finished upgrading the ip cores
Info: 2024.02.16.22:10:40 Info: Saving generation log to C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top
Info: 2024.02.16.22:10:40 Info: Starting: Create simulation model
Info: 2024.02.16.22:10:40 Info: qsys-generate C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top\simulation --family="Cyclone V" --part=5CEBA4F23C7
Info: 2024.02.16.22:10:40 Info: Loading Cyclone_V_NIOS_II
Info: 2024.02.16.22:10:41 Info: Reading input file
Info: 2024.02.16.22:10:41 Info: Adding clock [altera_clock_bridge 23.1]
Info: 2024.02.16.22:10:41 Info: Parameterizing module clock
Info: 2024.02.16.22:10:41 Info: Adding jtag_uart_0 [altera_avalon_jtag_uart 23.1]
Info: 2024.02.16.22:10:41 Info: Parameterizing module jtag_uart_0
Info: 2024.02.16.22:10:41 Info: Adding nios2_gen2_0 [altera_nios2_gen2 23.1]
Info: 2024.02.16.22:10:41 Info: Parameterizing module nios2_gen2_0
Info: 2024.02.16.22:10:41 Info: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 23.1]
Info: 2024.02.16.22:10:41 Info: Parameterizing module onchip_memory2_0
Info: 2024.02.16.22:10:41 Info: Adding pio_0 [altera_avalon_pio 23.1]
Info: 2024.02.16.22:10:41 Info: Parameterizing module pio_0
Info: 2024.02.16.22:10:41 Info: Adding reset [altera_reset_bridge 23.1]
Info: 2024.02.16.22:10:41 Info: Parameterizing module reset
Info: 2024.02.16.22:10:41 Info: Building connections
Info: 2024.02.16.22:10:41 Info: Parameterizing connections
Info: 2024.02.16.22:10:41 Info: Validating
Info: 2024.02.16.22:10:41 Info: Done reading input file
Info: 2024.02.16.22:10:43 Info: niosii_top.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Warning: 2024.02.16.22:10:43 Warning: niosii_top.nios2_gen2_0: Nios II cores are not recommended for new projects and are subject to removal in a future release. Nios V cores are the recommended replacement as applicable.
Info: 2024.02.16.22:10:43 Info: niosii_top: Generating niosii_top "niosii_top" for SIM_VERILOG
Info: 2024.02.16.22:10:49 Info: jtag_uart_0: Starting RTL generation for module 'niosii_top_jtag_uart_0'
Info: 2024.02.16.22:10:49 Info: jtag_uart_0: Generation command is [exec C:/intelfpga_lite/23.1std/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/23.1std/quartus/bin64/perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosii_top_jtag_uart_0 --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0002_jtag_uart_0_gen/ --quartus_dir=C:/intelfpga_lite/23.1std/quartus --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0002_jtag_uart_0_gen//niosii_top_jtag_uart_0_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0002_jtag_uart_0_gen
Info: 2024.02.16.22:10:50 Info: jtag_uart_0: Done RTL generation for module 'niosii_top_jtag_uart_0'
Info: 2024.02.16.22:10:50 Info: jtag_uart_0: "niosii_top" instantiated altera_avalon_jtag_uart "jtag_uart_0"
Info: 2024.02.16.22:10:51 Info: nios2_gen2_0: "niosii_top" instantiated altera_nios2_gen2 "nios2_gen2_0"
Info: 2024.02.16.22:10:51 Info: onchip_memory2_0: Starting RTL generation for module 'niosii_top_onchip_memory2_0'
Info: 2024.02.16.22:10:51 Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/23.1std/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/23.1std/quartus/bin64/perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosii_top_onchip_memory2_0 --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0003_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/23.1std/quartus --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0003_onchip_memory2_0_gen//niosii_top_onchip_memory2_0_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0003_onchip_memory2_0_gen
Info: 2024.02.16.22:10:51 Info: onchip_memory2_0: Done RTL generation for module 'niosii_top_onchip_memory2_0'
Info: 2024.02.16.22:10:52 Info: onchip_memory2_0: "niosii_top" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: 2024.02.16.22:10:52 Info: pio_0: Starting RTL generation for module 'niosii_top_pio_0'
Info: 2024.02.16.22:10:52 Info: pio_0: Generation command is [exec C:/intelfpga_lite/23.1std/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/23.1std/quartus/bin64/perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=niosii_top_pio_0 --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0004_pio_0_gen/ --quartus_dir=C:/intelfpga_lite/23.1std/quartus --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0004_pio_0_gen//niosii_top_pio_0_component_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0004_pio_0_gen
Info: 2024.02.16.22:10:52 Info: pio_0: Done RTL generation for module 'niosii_top_pio_0'
Info: 2024.02.16.22:10:52 Info: pio_0: "niosii_top" instantiated altera_avalon_pio "pio_0"
Info: 2024.02.16.22:10:57 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:10:57 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:10:58 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:10:59 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:11:02 Info: mm_interconnect_0: "niosii_top" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: 2024.02.16.22:11:02 Info: irq_mapper: "niosii_top" instantiated altera_irq_mapper "irq_mapper"
Info: 2024.02.16.22:11:02 Info: rst_controller: "niosii_top" instantiated altera_reset_controller "rst_controller"
Info: 2024.02.16.22:11:02 Info: cpu: Starting RTL generation for module 'niosii_top_nios2_gen2_0_cpu'
Info: 2024.02.16.22:11:02 Info: cpu: Generation command is [exec C:/intelFPGA_lite/23.1std/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/23.1std/quartus/bin64//perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=niosii_top_nios2_gen2_0_cpu --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0007_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/23.1std/quartus/bin64/ --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0007_cpu_gen//niosii_top_nios2_gen2_0_cpu_processor_configuration.pl --do_build_sim=1 --sim_dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0007_cpu_gen
Info: 2024.02.16.22:11:04 Info: cpu: # 2024.02.16 22:11:03 (*) Starting Nios II generation
Info: 2024.02.16.22:11:04 Info: cpu: # 2024.02.16 22:11:03 (*) Elaborating CPU configuration settings
Info: 2024.02.16.22:11:04 Info: cpu: # 2024.02.16 22:11:03 (*) Creating all objects for CPU
Info: 2024.02.16.22:11:04 Info: cpu: # 2024.02.16 22:11:03 (*) Creating 'C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0007_cpu_gen/
Info: 2024.02.16.22:11:04 Info: cpu: # 2024.02.16 22:11:03 (*) Generating RTL from CPU objects
Info: 2024.02.16.22:11:04 Info: cpu: # 2024.02.16 22:11:03 (*) Creating plain-text RTL
Info: 2024.02.16.22:11:04 Info: cpu: # 2024.02.16 22:11:04 (*) Done Nios II generation
Info: 2024.02.16.22:11:04 Info: cpu: Done RTL generation for module 'niosii_top_nios2_gen2_0_cpu'
Info: 2024.02.16.22:11:04 Info: cpu: "nios2_gen2_0" instantiated altera_nios2_gen2_unit "cpu"
Info: 2024.02.16.22:11:04 Info: nios2_gen2_0_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_0_data_master_translator"
Info: 2024.02.16.22:11:04 Info: jtag_uart_0_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_0_avalon_jtag_slave_translator"
Info: 2024.02.16.22:11:04 Info: nios2_gen2_0_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_0_data_master_agent"
Info: 2024.02.16.22:11:04 Info: jtag_uart_0_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_0_avalon_jtag_slave_agent"
Info: 2024.02.16.22:11:04 Info: jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo"
Info: 2024.02.16.22:11:04 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: 2024.02.16.22:11:04 Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: 2024.02.16.22:11:04 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: 2024.02.16.22:11:04 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: 2024.02.16.22:11:04 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: 2024.02.16.22:11:04 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: 2024.02.16.22:11:04 Info: Reusing file C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top/simulation/submodules
Info: 2024.02.16.22:11:05 Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: 2024.02.16.22:11:05 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: 2024.02.16.22:11:05 Info: niosii_top: Done "niosii_top" with 22 modules, 42 files
Info: 2024.02.16.22:11:05 Info: qsys-generate succeeded.
Info: 2024.02.16.22:11:05 Info: Finished: Create simulation model
Info: 2024.02.16.22:11:05 Info: Starting: Create Modelsim Project.
Info: 2024.02.16.22:11:05 Info: sim-script-gen --spd=C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top\niosii_top.spd --output-directory=C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top/simulation
Info: 2024.02.16.22:11:05 Info: Doing: ip-make-simscript --spd=C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top\niosii_top.spd --output-directory=C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top/simulation
Info: 2024.02.16.22:11:06 Info: Generating the following file(s) for RIVIERA simulator in C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top/simulation
Info: 2024.02.16.22:11:06 Info: aldec
Info: 2024.02.16.22:11:06 Info: Generating the following file(s) for MODELSIM simulator in C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top/simulation
Info: 2024.02.16.22:11:06 Info: mentor
Info: 2024.02.16.22:11:06 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top/simulation
Info: 2024.02.16.22:11:06 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: 2024.02.16.22:11:06 Info: Finished: Create Modelsim Project.
Info: 2024.02.16.22:11:06 Info: Starting: Create block symbol file (.bsf)
Info: 2024.02.16.22:11:06 Info: qsys-generate C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top.qsys --block-symbol-file --output-directory=C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top --family="Cyclone V" --part=5CEBA4F23C7
Info: 2024.02.16.22:11:06 Info: Loading Cyclone_V_NIOS_II
Info: 2024.02.16.22:11:07 Info: Reading input file
Info: 2024.02.16.22:11:07 Info: Adding clock [altera_clock_bridge 23.1]
Info: 2024.02.16.22:11:07 Info: Parameterizing module clock
Info: 2024.02.16.22:11:07 Info: Adding jtag_uart_0 [altera_avalon_jtag_uart 23.1]
Info: 2024.02.16.22:11:07 Info: Parameterizing module jtag_uart_0
Info: 2024.02.16.22:11:07 Info: Adding nios2_gen2_0 [altera_nios2_gen2 23.1]
Info: 2024.02.16.22:11:07 Info: Parameterizing module nios2_gen2_0
Info: 2024.02.16.22:11:07 Info: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 23.1]
Info: 2024.02.16.22:11:07 Info: Parameterizing module onchip_memory2_0
Info: 2024.02.16.22:11:07 Info: Adding pio_0 [altera_avalon_pio 23.1]
Info: 2024.02.16.22:11:07 Info: Parameterizing module pio_0
Info: 2024.02.16.22:11:07 Info: Adding reset [altera_reset_bridge 23.1]
Info: 2024.02.16.22:11:07 Info: Parameterizing module reset
Info: 2024.02.16.22:11:07 Info: Building connections
Info: 2024.02.16.22:11:07 Info: Parameterizing connections
Info: 2024.02.16.22:11:07 Info: Validating
Info: 2024.02.16.22:11:07 Info: Done reading input file
Info: 2024.02.16.22:11:09 Info: niosii_top.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Warning: 2024.02.16.22:11:09 Warning: niosii_top.nios2_gen2_0: Nios II cores are not recommended for new projects and are subject to removal in a future release. Nios V cores are the recommended replacement as applicable.
Info: 2024.02.16.22:11:09 Info: qsys-generate succeeded.
Info: 2024.02.16.22:11:09 Info: Finished: Create block symbol file (.bsf)
Info: 2024.02.16.22:11:09 Info:
Info: 2024.02.16.22:11:09 Info: Starting: Create HDL design files for synthesis
Info: 2024.02.16.22:11:09 Info: qsys-generate C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top.qsys --synthesis=VERILOG --output-directory=C:\Users\jongh\Documents\repo\Cyclone_V_NIOS_II\niosii_top\synthesis --family="Cyclone V" --part=5CEBA4F23C7
Info: 2024.02.16.22:11:09 Info: Loading Cyclone_V_NIOS_II
Info: 2024.02.16.22:11:10 Info: Reading input file
Info: 2024.02.16.22:11:10 Info: Adding clock [altera_clock_bridge 23.1]
Info: 2024.02.16.22:11:10 Info: Parameterizing module clock
Info: 2024.02.16.22:11:10 Info: Adding jtag_uart_0 [altera_avalon_jtag_uart 23.1]
Info: 2024.02.16.22:11:10 Info: Parameterizing module jtag_uart_0
Info: 2024.02.16.22:11:10 Info: Adding nios2_gen2_0 [altera_nios2_gen2 23.1]
Info: 2024.02.16.22:11:10 Info: Parameterizing module nios2_gen2_0
Info: 2024.02.16.22:11:10 Info: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 23.1]
Info: 2024.02.16.22:11:10 Info: Parameterizing module onchip_memory2_0
Info: 2024.02.16.22:11:10 Info: Adding pio_0 [altera_avalon_pio 23.1]
Info: 2024.02.16.22:11:10 Info: Parameterizing module pio_0
Info: 2024.02.16.22:11:10 Info: Adding reset [altera_reset_bridge 23.1]
Info: 2024.02.16.22:11:10 Info: Parameterizing module reset
Info: 2024.02.16.22:11:10 Info: Building connections
Info: 2024.02.16.22:11:10 Info: Parameterizing connections
Info: 2024.02.16.22:11:10 Info: Validating
Info: 2024.02.16.22:11:10 Info: Done reading input file
Info: 2024.02.16.22:11:12 Info: niosii_top.jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Warning: 2024.02.16.22:11:12 Warning: niosii_top.nios2_gen2_0: Nios II cores are not recommended for new projects and are subject to removal in a future release. Nios V cores are the recommended replacement as applicable.
Info: 2024.02.16.22:11:12 Info: niosii_top: Generating niosii_top "niosii_top" for QUARTUS_SYNTH
Info: 2024.02.16.22:11:17 Info: jtag_uart_0: Starting RTL generation for module 'niosii_top_jtag_uart_0'
Info: 2024.02.16.22:11:17 Info: jtag_uart_0: Generation command is [exec C:/intelfpga_lite/23.1std/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/23.1std/quartus/bin64/perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=niosii_top_jtag_uart_0 --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0021_jtag_uart_0_gen/ --quartus_dir=C:/intelfpga_lite/23.1std/quartus --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0021_jtag_uart_0_gen/
Info: 2024.02.16.22:11:17 Info: jtag_uart_0: Done RTL generation for module 'niosii_top_jtag_uart_0'
Info: 2024.02.16.22:11:17 Info: jtag_uart_0: "niosii_top" instantiated altera_avalon_jtag_uart "jtag_uart_0"
Info: 2024.02.16.22:11:18 Info: nios2_gen2_0: "niosii_top" instantiated altera_nios2_gen2 "nios2_gen2_0"
Info: 2024.02.16.22:11:18 Info: onchip_memory2_0: Starting RTL generation for module 'niosii_top_onchip_memory2_0'
Info: 2024.02.16.22:11:18 Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/23.1std/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/23.1std/quartus/bin64/perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=niosii_top_onchip_memory2_0 --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0022_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/23.1std/quartus --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0022_onchip_memory2_0_gen/
Info: 2024.02.16.22:11:19 Info: onchip_memory2_0: Done RTL generation for module 'niosii_top_onchip_memory2_0'
Info: 2024.02.16.22:11:19 Info: onchip_memory2_0: "niosii_top" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: 2024.02.16.22:11:19 Info: pio_0: Starting RTL generation for module 'niosii_top_pio_0'
Info: 2024.02.16.22:11:19 Info: pio_0: Generation command is [exec C:/intelfpga_lite/23.1std/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/23.1std/quartus/bin64/perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=niosii_top_pio_0 --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0023_pio_0_gen/ --quartus_dir=C:/intelfpga_lite/23.1std/quartus --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0023_pio_0_gen/
Info: 2024.02.16.22:11:19 Info: pio_0: Done RTL generation for module 'niosii_top_pio_0'
Info: 2024.02.16.22:11:19 Info: pio_0: "niosii_top" instantiated altera_avalon_pio "pio_0"
Info: 2024.02.16.22:11:24 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:11:24 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:11:25 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:11:25 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: 2024.02.16.22:11:29 Info: mm_interconnect_0: "niosii_top" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: 2024.02.16.22:11:29 Info: irq_mapper: "niosii_top" instantiated altera_irq_mapper "irq_mapper"
Info: 2024.02.16.22:11:29 Info: rst_controller: "niosii_top" instantiated altera_reset_controller "rst_controller"
Info: 2024.02.16.22:11:29 Info: cpu: Starting RTL generation for module 'niosii_top_nios2_gen2_0_cpu'
Info: 2024.02.16.22:11:29 Info: cpu: Generation command is [exec C:/intelFPGA_lite/23.1std/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/23.1std/quartus/bin64//perl/lib -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/23.1std/quartus/sopc_builder/bin -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/23.1std/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.pl --name=niosii_top_nios2_gen2_0_cpu --dir=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0026_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/23.1std/quartus/bin64/ --verilog --config=C:/Users/jongh/AppData/Local/Temp/alt9769_7289600530812729082.dir/0026_cpu_gen/
Info: 2024.02.16.22:11:30 Info: cpu: # 2024.02.16 22:11:29 (*) Starting Nios II generation
Info: 2024.02.16.22:11:30 Info: cpu: # 2024.02.16 22:11:29 (*) Elaborating CPU configuration settings
Info: 2024.02.16.22:11:30 Info: cpu: # 2024.02.16 22:11:29 (*) Creating all objects for CPU
Info: 2024.02.16.22:11:30 Info: cpu: # 2024.02.16 22:11:30 (*) Generating RTL from CPU objects
Info: 2024.02.16.22:11:30 Info: cpu: # 2024.02.16 22:11:30 (*) Creating plain-text RTL
Info: 2024.02.16.22:11:30 Info: cpu: # 2024.02.16 22:11:30 (*) Done Nios II generation
Info: 2024.02.16.22:11:30 Info: cpu: Done RTL generation for module 'niosii_top_nios2_gen2_0_cpu'
Info: 2024.02.16.22:11:30 Info: cpu: "nios2_gen2_0" instantiated altera_nios2_gen2_unit "cpu"
Info: 2024.02.16.22:11:30 Info: nios2_gen2_0_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_0_data_master_translator"
Info: 2024.02.16.22:11:30 Info: jtag_uart_0_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_0_avalon_jtag_slave_translator"
Info: 2024.02.16.22:11:30 Info: nios2_gen2_0_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_0_data_master_agent"
Info: 2024.02.16.22:11:30 Info: jtag_uart_0_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_0_avalon_jtag_slave_agent"
Info: 2024.02.16.22:11:30 Info: jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo"
Info: 2024.02.16.22:11:30 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: 2024.02.16.22:11:30 Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: 2024.02.16.22:11:30 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: 2024.02.16.22:11:30 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: 2024.02.16.22:11:30 Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: 2024.02.16.22:11:30 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: 2024.02.16.22:11:30 Info: Reusing file C:/Users/jongh/Documents/repo/Cyclone_V_NIOS_II/niosii_top/synthesis/submodules
Info: 2024.02.16.22:11:32 Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: 2024.02.16.22:11:32 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: 2024.02.16.22:11:32 Info: niosii_top: Done "niosii_top" with 22 modules, 35 files
Info: 2024.02.16.22:11:32 Info: qsys-generate succeeded.
Info: 2024.02.16.22:11:32 Info: Finished: Create HDL design files for synthesis
Info (11131): Completed upgrading IP component Qsys with file "niosii_top.qsys"
Info (23030): Evaluation of Tcl script c:/intelfpga_lite/23.1std/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 4870 megabytes
Info: Processing ended: Fri Feb 16 22:11:32 2024
Info: Elapsed time: 00:01:12
Info: Total CPU time (on all processors): 00:00:33