From 6b69dcff68e14701bdd72eccb641a320445bf266 Mon Sep 17 00:00:00 2001
From: tinyu <tinyu0806@gmail.com>
Date: Fri, 6 Nov 2026 18:16:50 +0800
Subject: [PATCH] board_spec: correct the StamP4XHub signal A/B roles

The factory pinmap puts signal A on the lower GPIO of each connector:
Grove12 GPIO37 (A) / GPIO38 (B), Grove13 GPIO0 (A, SDA) / GPIO1 (B, SCL)
and Grove14 GPIO26 (A) / GPIO27 (B). The catalog had the two pins of each
connector the other way round; the note on each pin already stated the order
the pinmap uses.

Grove15 (GPIO3 / GPIO2) is correct and unchanged. Nothing in M5Unified
depends on this, the catalog is the only wrong copy.

Signed-off-by: tinyu <tinyu0806@gmail.com>
---
 extras/board_spec/boards/m5stampp4xhub.json   | 16 ++++++++--------
 extras/board_spec/dist/board_spec_editor.html |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/extras/board_spec/boards/m5stampp4xhub.json b/extras/board_spec/boards/m5stampp4xhub.json
index 60ca2878..feb6de6c 100644
--- a/extras/board_spec/boards/m5stampp4xhub.json
+++ b/extras/board_spec/boards/m5stampp4xhub.json
@@ -32,7 +32,7 @@
       "roles": [
         "bus:internal_i2c.sda",
         "bus:touch_i2c.sda",
-        "conn:grove13.2"
+        "conn:grove13.1"
       ],
       "pull": "up",
       "note": "Main I2C SDA (R42 2.2K to VSYS_3V3); shared by PM1, IOE1, INA226, touch and Grove13.",
@@ -44,7 +44,7 @@
       "roles": [
         "bus:internal_i2c.scl",
         "bus:touch_i2c.scl",
-        "conn:grove13.1"
+        "conn:grove13.2"
       ],
       "pull": "up",
       "note": "Main I2C SCL (R43 2.2K to VSYS_3V3); shared by PM1, IOE1, INA226, touch and Grove13.",
@@ -168,15 +168,15 @@
     },
     "26": {
       "roles": [
-        "conn:grove14.2"
+        "conn:grove14.1"
       ],
-      "note": "USB1 D- (module G26_USB1_N); Grove14 signal B."
+      "note": "USB1 D- (module G26_USB1_N); Grove14 signal A."
     },
     "27": {
       "roles": [
-        "conn:grove14.1"
+        "conn:grove14.2"
       ],
-      "note": "USB1 D+ (module G27_USB1_P); Grove14 signal A."
+      "note": "USB1 D+ (module G27_USB1_P); Grove14 signal B."
     },
     "28": {
       "roles": [],
@@ -217,13 +217,13 @@
     },
     "37": {
       "roles": [
-        "conn:grove12.2"
+        "conn:grove12.1"
       ],
       "note": "UART0 TX; Grove12 signal A."
     },
     "38": {
       "roles": [
-        "conn:grove12.1"
+        "conn:grove12.2"
       ],
       "note": "UART0 RX; Grove12 signal B."
     },
diff --git a/extras/board_spec/dist/board_spec_editor.html b/extras/board_spec/dist/board_spec_editor.html
index 10fb2038..5e6ff4c3 100644
--- a/extras/board_spec/dist/board_spec_editor.html
+++ b/extras/board_spec/dist/board_spec_editor.html
@@ -1060,7 +1060,7 @@ <h2 id="board-dialog-title"></h2>
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SCL/SDA, PHY_RST/INT and SPI signals share internal peripherals. Isolated input, relay, CAN and RS485 terminals are not direct GPIO connections and are outside this catalog entry.","verified":{"positions":"datasheet"}},"grove_c":{"type":"hy2_4p","standard":"port_uart","note":"Product marking is PORT.C: white GPIO4, yellow GPIO5, red 5V, black GND. M5Unified does not assign StamPLC Port C in its package pin table, so this is cataloged as the physical grove_c connector rather than the port_c contract name."}}},"m5stampp4":{"schema_version":1,"id":"m5stampp4","name":"M5StampP4","official_name":"M5Stack Stamp-P4","official_name_verified":true,"legacy_board_id":150,"chip":"esp32p4","spec":{"links":{"product":"https://docs.m5stack.com/en/core/Stamp-P4","schematic":"https://m5stack-doc.oss-cn-shenzhen.aliyuncs.com/1218/SCH_Stamp-P4_2026_03_16_17_23_06.pdf","verified":{"product":"datasheet","schematic":"datasheet"}}},"pins":{"0":{"roles":["conn:stamp_pads.11"],"verified":{"roles":"datasheet"}},"1":{"roles":["conn:stamp_pads.9"],"verified":{"roles":"datasheet"}},"2":{"roles":["conn:stamp_pads.37"],"verified":{"roles":"datasheet"}},"3":{"roles":["conn:stamp_pads.45"],"verified":{"roles":"datasheet"}},"4":{"roles":["conn:stamp_pads.16"],"verified":{"roles":"datasheet"}},"5":{"roles":["conn:stamp_pads.35"],"verified":{"roles":"datasheet"}},"6":{"roles":["conn:stamp_pads.18"],"verified":{"roles":"datasheet"}},"7":{"roles":["conn:stamp_pads.8"],"verified":{"roles":"datasheet"}},"8":{"roles":["conn:stamp_pads.7"],"verified":{"roles":"datasheet"}},"9":{"roles":["conn:stamp_pads.6","conn:camera_btb.16","conn:sdio_btb.14"],"verified":{"roles":"datasheet"}},"10":{"roles":["conn:stamp_pads.5"],"verified":{"roles":"datasheet"}},"11":{"roles":["conn:stamp_pads.4","conn:camera_btb.15","conn:sdio_btb.16"],"verified":{"roles":"datasheet"}},"12":{"roles":["conn:stamp_pads.3"],"verified":{"roles":"datasheet"}},"13":{"roles":["conn:stamp_pads.29"],"verified":{"roles":"datasheet"}},"14":{"roles":["conn:stamp_pads.2"],"verified":{"roles":"datasheet"}},"15":{"roles":["conn:stamp_pads.1"],"verified":{"roles":"datasheet"}},"16":{"roles":["conn:stamp_pads.27"],"verified":{"roles":"datasheet"}},"17":{"roles":["conn:stamp_pads.26"],"verified":{"roles":"datasheet"}},"18":{"roles":["conn:stamp_pads.25"],"verified":{"roles":"datasheet"}},"19":{"roles":["conn:stamp_pads.24"],"verified":{"roles":"datasheet"}},"20":{"roles":["conn:stamp_pads.23"],"verified":{"roles":"datasheet"}},"21":{"roles":["conn:stamp_pads.22"],"verified":{"roles":"datasheet"}},"22":{"roles":["conn:stamp_pads.21"],"verified":{"roles":"datasheet"}},"23":{"roles":["conn:stamp_pads.20"],"verified":{"roles":"datasheet"}},"26":{"roles":["conn:stamp_pads.19"],"verified":{"roles":"datasheet"}},"27":{"roles":["conn:stamp_pads.17"],"verified":{"roles":"datasheet"}},"28":{"roles":["conn:stamp_pads.52"],"verified":{"roles":"datasheet"}},"29":{"roles":["conn:stamp_pads.54"],"verified":{"roles":"datasheet"}},"30":{"roles":["conn:stamp_pads.53"],"verified":{"roles":"datasheet"}},"31":{"roles":["conn:stamp_pads.51"],"verified":{"roles":"datasheet"}},"32":{"roles":["conn:stamp_pads.46"],"verified":{"roles":"datasheet"}},"33":{"roles":["conn:stamp_pads.50"],"verified":{"roles":"datasheet"}},"34":{"roles":["conn:stamp_pads.33"],"verified":{"roles":"datasheet"}},"35":{"roles":["conn:stamp_pads.36","conn:stamp_pads.48"],"verified":{"roles":"datasheet"}},"36":{"roles":["conn:stamp_pads.47"],"verified":{"roles":"datasheet"}},"37":{"roles":["conn:stamp_pads.30"],"verified":{"roles":"datasheet"}},"38":{"roles":["conn:stamp_pads.32"],"verified":{"roles":"datasheet"}},"39":{"roles":["conn:stamp_pads.31"],"verified":{"roles":"datasheet"}},"40":{"roles":["conn:sdio_btb.19"],"verified":{"roles":"datasheet"}},"41":{"roles":["conn:stamp_pads.49"],"verified":{"roles":"datasheet"}},"42":{"roles":["conn:sdio_btb.5"],"verified":{"roles":"datasheet"}},"43":{"roles":["conn:sdio_btb.7"],"verified":{"roles":"datasheet"}},"44":{"roles":["conn:sdio_btb.9"],"verified":{"roles":"datasheet"}},"45":{"roles":["conn:sdio_btb.13"],"verified":{"roles":"datasheet"}},"46":{"roles":["conn:sdio_btb.11"],"verified":{"roles":"datasheet"}},"47":{"roles":["conn:sdio_btb.15"],"verified":{"roles":"datasheet"}},"48":{"roles":["conn:sdio_btb.17"],"verified":{"roles":"datasheet"}},"49":{"roles":["conn:stamp_pads.12"],"verified":{"roles":"datasheet"}},"50":{"roles":["conn:stamp_pads.10"],"verified":{"roles":"datasheet"}},"51":{"roles":["conn:sdio_btb.12"],"verified":{"roles":"datasheet"}},"52":{"roles":["conn:stamp_pads.55"],"verified":{"roles":"datasheet"}},"53":{"roles":["conn:camera_btb.3"],"verified":{"roles":"datasheet"}},"54":{"roles":["conn:camera_btb.2"],"verified":{"roles":"datasheet"}}},"buses":{},"devices":{},"connectors":{"stamp_pads":{"type":"logical_terminals_65","positions":{"13":"pwr:gnd","14":"pwr:5vin","15":"pwr:vbus","28":"pwr:3v3","34":"chip:en","38":"pwr:gnd","39":"pwr:sys_5v","40":"fixed:usb2.dp","41":"fixed:usb2.dn","42":"pwr:gnd","43":"chip:usb_dn","44":"chip:usb_dp","56":"pwr:gnd","57":"fixed:mipi_dsi.d0n","58":"fixed:mipi_dsi.d0p","59":"pwr:gnd","60":"fixed:mipi_dsi.clkp","61":"fixed:mipi_dsi.clkn","62":"pwr:gnd","63":"fixed:mipi_dsi.d1n","64":"fixed:mipi_dsi.d1p","65":"pwr:gnd"},"note":"Numbers 1-65 follow STAMP1 in the official schematic. This logical order does not imply a uniform physical pitch. GPIO24/25 are represented as dedicated native USB D-/D+ endpoints; USB2_HOST and MIPI DSI pads are dedicated non-GPIO signals. GPIO35 reaches two pads (36 and 48).","verified":{"positions":"datasheet"},"shared_gpio":["36","48"]},"camera_btb":{"type":"logical_terminals_20","positions":{"1":"pwr:gnd","4":"pwr:gnd","5":"fixed:mipi_csi.d0n","6":"fixed:mipi_csi.d0p","7":"pwr:gnd","8":"fixed:mipi_csi.clkn","9":"fixed:mipi_csi.clkp","10":"pwr:gnd","11":"pwr:gnd","12":"fixed:mipi_csi.d1n","13":"fixed:mipi_csi.d1p","14":"pwr:3v3","17":"pwr:gnd","18":"pwr:gnd","19":"pwr:gnd","20":"pwr:gnd"},"note":"Exposed MIPI CSI camera BTB connector J2; terminal numbering follows the official schematic and PinMap. GPIO54=CAM_RST, GPIO53=CAM_MCLK, GPIO11=SDA, GPIO9=SCL.","verified":{"positions":"datasheet"}},"sdio_btb":{"type":"logical_terminals_20","positions":{"1":"pwr:gnd","2":"pwr:gnd","3":"pwr:gnd","4":"pwr:sys_5v","6":"pwr:sys_5v","8":"pwr:3v3","10":"pwr:3v3","18":"pwr:gnd","20":"pwr:gnd"},"note":"Exposed 20-pin SDIO BTB connector J3. Numbers follow the official schematic/PinMap. GPIO42 is SDIO_RST, GPIO43 CLK, GPIO44 CMD, GPIO45/46/47/48 D0/D1/D2/D3.","verified":{"positions":"datasheet"}}}},"m5stampp4x":{"schema_version":1,"id":"m5stampp4x","name":"M5StampP4X","official_name":"M5StampP4X","legacy_board_id":156,"chip":"esp32p4","pins":{},"buses":{},"devices":{}},"m5stampp4xhub":{"schema_version":1,"id":"m5stampp4xhub","name":"M5StamP4XHub","official_name":"M5Stack StampP4X Hub","aliases":["stampp4x hub","stampp4xhub","stamp p4x hub"],"legacy_board_id":157,"chip":"esp32p4","spec":{"display":{"resolution":[720,1280],"touch":true},"storage":{"psram_mb":32,"psram_mode":"opi","flash_mb":16},"power":{"pmic_part":"M5PM1"}},"pins":{"0":{"roles":["bus:internal_i2c.sda","bus:touch_i2c.sda","conn:grove13.2"],"pull":"up","note":"Main I2C SDA (R42 2.2K to VSYS_3V3); shared by PM1, IOE1, INA226, touch and Grove13.","verified":{"roles":"generated"}},"1":{"roles":["bus:internal_i2c.scl","bus:touch_i2c.scl","conn:grove13.1"],"pull":"up","note":"Main I2C SCL (R43 2.2K to VSYS_3V3); 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the PM1 is addressed on the internal bus."},"pmic":{"kind":"pmic","part":"m5pm1","bus":"internal_i2c","note":"PM1 also drives the RGB LED, Grove15 5V, USB-A 5V and the CHIP_EN gate."},"ioe":{"kind":"io_expander","part":"m5ioe1","bus":"internal_i2c","note":"IOE1 switches the 5V rail of Grove0-11, 13 and 14."},"ina226":{"kind":"sensor","bus":"internal_i2c","i2c_addr":"0x40","note":"INA226 with 5 mOhm shunt on the Grove 5V rail (A0/A1 grounded)."},"rgb_led":{"kind":"led","note":"RGB LED behind the PM1: red on LED_EN (active high), green on PM1 GPIO4, blue on PM1 GPIO0 (both active low)."},"psram":{"kind":"psram","part":"psram"}},"connectors":{"grove0":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG6."},"grove1":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG7."},"grove2":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG14."},"grove3":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG1."},"grove4":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG5."},"grove5":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG10."},"grove6":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG12."},"grove7":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG11."},"grove8":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG4."},"grove9":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG13."},"grove10":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG9."},"grove11":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG2."},"grove12":{"type":"hy2_4p","standard":"port_uart","note":"UART0 console on signal A (TX, GPIO37) and signal B (RX, GPIO38). The 5V rail is the PM1 CHG_EN output and has no separate software enable."},"grove13":{"type":"hy2_4p","standard":"port_i2c","note":"External I2C on the system bus (SCL GPIO1, SDA GPIO0, 2.2K pull-ups). Signal A is SDA and signal B is SCL; the 5V rail is switched by M5IOE1 IOEG3 and also feeds the I2C level shifter."},"grove14":{"type":"hy2_4p","standard":"port_io","note":"USB1 D+ / D-; do not use as GPIO while USB1 is active. 5V rail switched by M5IOE1 IOEG8."},"grove15":{"type":"hy2_4p","standard":"port_io","note":"Shared with LCD_RST/TP_RST (signal A, GPIO3) and TP_INT (signal B, GPIO2); using this port can reset the panel or lose touch. 5V rail switched by PM1 GPIO2."}}},"m5stamppico":{"schema_version":1,"id":"m5stamppico","name":"M5StampPico","official_name":"M5Stack Stamp-Pico","official_name_verified":true,"legacy_board_id":133,"chip":"esp32_d0wdq6","spec":{"links":{"product":"https://docs.m5stack.com/en/core/Stamp-Pico","schematic":"https://static-cdn.m5stack.com/resource/docs/products/core/stamp_pico/stamp_pico_sch_01.webp","verified":{"product":"datasheet","schematic":"datasheet"}}},"pins":{"0":{"roles":["conn:stamp_right.5"],"verified":{"roles":"datasheet"}},"1":{"roles":["conn:stamp_right.2"],"verified":{"roles":"datasheet"}},"3":{"roles":["conn:stamp_right.3"],"verified":{"roles":"datasheet"}},"18":{"roles":["conn:stamp_left.3"],"verified":{"roles":"datasheet"}},"19":{"roles":["conn:stamp_left.4"],"verified":{"roles":"datasheet"}},"21":{"roles":["bus:internal_i2c.sda","conn:stamp_left.5"],"verified":{"roles":"generated"}},"22":{"roles":["bus:internal_i2c.scl","conn:stamp_left.6"],"verified":{"roles":"generated"}},"25":{"roles":["conn:stamp_left.7"],"verified":{"roles":"datasheet"}},"26":{"roles":["conn:stamp_left.1"],"verified":{"roles":"datasheet"}},"27":{"roles":["dev:rgb_led.data"],"verified":{"roles":"generated"}},"32":{"roles":["conn:port_a.2"],"verified":{"roles":"generated"}},"33":{"roles":["conn:port_a.1"],"verified":{"roles":"generated"}},"36":{"roles":["conn:stamp_left.2"],"verified":{"roles":"datasheet"}}},"buses":{"internal_i2c":{"kind":"i2c","signals":["sda","scl"],"preferred_host":1,"fixed":false,"verified":{"signals":"generated","preferred_host":"generated"}}},"devices":{"rgb_led":{"kind":"led_strip"}},"connectors":{"port_a":{"type":"hy2_4p","standard":"port_i2c","note":"Grove solder footprint shown at the bottom of the official PinMap; the connector may be fitted separately. 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This logical order does not imply a uniform physical pitch. GPIO24/25 are represented as dedicated native USB D-/D+ endpoints; USB2_HOST and MIPI DSI pads are dedicated non-GPIO signals. GPIO35 reaches two pads (36 and 48).","verified":{"positions":"datasheet"},"shared_gpio":["36","48"]},"camera_btb":{"type":"logical_terminals_20","positions":{"1":"pwr:gnd","4":"pwr:gnd","5":"fixed:mipi_csi.d0n","6":"fixed:mipi_csi.d0p","7":"pwr:gnd","8":"fixed:mipi_csi.clkn","9":"fixed:mipi_csi.clkp","10":"pwr:gnd","11":"pwr:gnd","12":"fixed:mipi_csi.d1n","13":"fixed:mipi_csi.d1p","14":"pwr:3v3","17":"pwr:gnd","18":"pwr:gnd","19":"pwr:gnd","20":"pwr:gnd"},"note":"Exposed MIPI CSI camera BTB connector J2; terminal numbering follows the official schematic and PinMap. GPIO54=CAM_RST, GPIO53=CAM_MCLK, GPIO11=SDA, GPIO9=SCL.","verified":{"positions":"datasheet"}},"sdio_btb":{"type":"logical_terminals_20","positions":{"1":"pwr:gnd","2":"pwr:gnd","3":"pwr:gnd","4":"pwr:sys_5v","6":"pwr:sys_5v","8":"pwr:3v3","10":"pwr:3v3","18":"pwr:gnd","20":"pwr:gnd"},"note":"Exposed 20-pin SDIO BTB connector J3. Numbers follow the official schematic/PinMap. GPIO42 is SDIO_RST, GPIO43 CLK, GPIO44 CMD, GPIO45/46/47/48 D0/D1/D2/D3.","verified":{"positions":"datasheet"}}}},"m5stampp4x":{"schema_version":1,"id":"m5stampp4x","name":"M5StampP4X","official_name":"M5StampP4X","legacy_board_id":156,"chip":"esp32p4","pins":{},"buses":{},"devices":{}},"m5stampp4xhub":{"schema_version":1,"id":"m5stampp4xhub","name":"M5StamP4XHub","official_name":"M5Stack StampP4X Hub","aliases":["stampp4x hub","stampp4xhub","stamp p4x hub"],"legacy_board_id":157,"chip":"esp32p4","spec":{"display":{"resolution":[720,1280],"touch":true},"storage":{"psram_mb":32,"psram_mode":"opi","flash_mb":16},"power":{"pmic_part":"M5PM1"}},"pins":{"0":{"roles":["bus:internal_i2c.sda","bus:touch_i2c.sda","conn:grove13.1"],"pull":"up","note":"Main I2C SDA (R42 2.2K to VSYS_3V3); shared by PM1, IOE1, INA226, touch and Grove13.","verified":{"roles":"generated"}},"1":{"roles":["bus:internal_i2c.scl","bus:touch_i2c.scl","conn:grove13.2"],"pull":"up","note":"Main I2C SCL (R43 2.2K to VSYS_3V3); shared by PM1, IOE1, INA226, touch and Grove13.","verified":{"roles":"generated"}},"2":{"roles":["dev:touch.int","conn:grove15.2"],"note":"Touch TP_INT through R68 0R; also Grove15 signal B."},"3":{"roles":["dev:lcd.rst","conn:grove15.1"],"note":"Shared LCD_RST / TP_RST through R71/R67 0R; also Grove15 signal A."},"4":{"roles":["conn:grove10.1"]},"5":{"roles":["conn:grove10.2"]},"6":{"roles":["conn:grove3.2"]},"7":{"roles":["conn:grove6.2"]},"8":{"roles":["conn:grove2.2"]},"9":{"roles":["conn:grove4.2"]},"10":{"roles":["conn:grove9.2"]},"11":{"roles":["conn:grove8.2"]},"12":{"roles":["conn:grove0.2"]},"13":{"roles":["conn:grove7.2"]},"14":{"roles":["conn:grove5.2"]},"15":{"roles":["conn:grove1.2"]},"16":{"roles":["conn:grove2.1"]},"17":{"roles":["conn:grove4.1"]},"18":{"roles":["conn:grove9.1"]},"19":{"roles":["conn:grove8.1"]},"20":{"roles":["conn:grove0.1"]},"21":{"roles":["conn:grove7.1"]},"22":{"roles":["conn:grove5.1"]},"23":{"roles":["conn:grove1.1"]},"26":{"roles":["conn:grove14.1"],"note":"USB1 D- (module G26_USB1_N); Grove14 signal A."},"27":{"roles":["conn:grove14.2"],"note":"USB1 D+ (module G27_USB1_P); Grove14 signal B."},"28":{"roles":[],"note":"Ethernet RMII RXDV (IP101GRI PHY address 1)."},"29":{"roles":[],"note":"Ethernet RMII RXD0."},"30":{"roles":[],"note":"Ethernet RMII RXD1."},"31":{"roles":[],"note":"Ethernet RMII MDC."},"32":{"roles":[],"note":"Ethernet RMII REF_CLK (50 MHz)."},"33":{"roles":[],"note":"Ethernet RMII TX_EN."},"34":{"roles":["conn:grove11.1"]},"35":{"roles":[],"note":"Ethernet RMII TXD1; also a boot strapping pin."},"36":{"roles":[],"note":"Ethernet RMII MDIO (1.5K pull-up to PHY_3V3)."},"37":{"roles":["conn:grove12.1"],"note":"UART0 TX; Grove12 signal A."},"38":{"roles":["conn:grove12.2"],"note":"UART0 RX; Grove12 signal B."},"39":{"roles":["conn:grove11.2"]},"41":{"roles":[],"note":"Ethernet RMII TXD0."},"49":{"roles":["conn:grove3.1"]},"50":{"roles":["conn:grove6.1"]},"52":{"roles":[],"note":"IP101GRI PHY reset."}},"buses":{"display_dsi":{"kind":"dsi","signals":[],"preferred_host":0,"lane_num":2,"freq":1040,"ldo_chan_id":3,"ldo_voltage_mv":2500,"fixed":true},"internal_i2c":{"kind":"i2c","signals":["sda","scl"],"preferred_host":1,"freq":100000,"fixed":true,"verified":{"signals":"generated","preferred_host":"generated","freq":"generated"}},"touch_i2c":{"kind":"i2c","signals":["sda","scl"],"preferred_host":1,"freq":400000,"fixed":true,"verified":{"signals":"generated","preferred_host":"generated","freq":"generated"}}},"devices":{"lcd":{"kind":"display","bus":"display_dsi","selected_by":"runtime","default":"st7123","choices":{"st7121":{"part":"st7121","spec":{"width":720,"height":1280,"memory_width":720,"memory_height":1280,"rotation_offset":0,"readable":true,"rgb_order":true,"dpi_freq_mhz":70,"hsync_back_porch":40,"hsync_pulse_width":2,"hsync_front_porch":40,"vsync_back_porch":24,"vsync_pulse_width":20,"vsync_front_porch":200}},"st7123":{"part":"st7123","spec":{"width":720,"height":1280,"memory_width":720,"memory_height":1280,"rotation_offset":0,"readable":true,"rgb_order":true,"dpi_freq_mhz":80,"hsync_back_porch":40,"hsync_pulse_width":2,"hsync_front_porch":40,"vsync_back_porch":8,"vsync_pulse_width":2,"vsync_front_porch":220}}}},"touch":{"kind":"touch","part":"st7123_touch","bus":"touch_i2c","i2c_addr":"0x55","spec":{"x_max":719,"y_max":1279,"rotation_offset":0}},"backlight":{"kind":"backlight","bus":"internal_i2c","i2c_addr":"0x6E","note":"LCD backlight enable is PM1 GPIO3 (PWM channel 0, 5 kHz, 12-bit); the PM1 is addressed on the internal bus."},"pmic":{"kind":"pmic","part":"m5pm1","bus":"internal_i2c","note":"PM1 also drives the RGB LED, Grove15 5V, USB-A 5V and the CHIP_EN gate."},"ioe":{"kind":"io_expander","part":"m5ioe1","bus":"internal_i2c","note":"IOE1 switches the 5V rail of Grove0-11, 13 and 14."},"ina226":{"kind":"sensor","bus":"internal_i2c","i2c_addr":"0x40","note":"INA226 with 5 mOhm shunt on the Grove 5V rail (A0/A1 grounded)."},"rgb_led":{"kind":"led","note":"RGB LED behind the PM1: red on LED_EN (active high), green on PM1 GPIO4, blue on PM1 GPIO0 (both active low)."},"psram":{"kind":"psram","part":"psram"}},"connectors":{"grove0":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG6."},"grove1":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG7."},"grove2":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG14."},"grove3":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG1."},"grove4":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG5."},"grove5":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG10."},"grove6":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG12."},"grove7":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG11."},"grove8":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG4."},"grove9":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG13."},"grove10":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG9."},"grove11":{"type":"hy2_4p","standard":"port_io","note":"5V rail switched by M5IOE1 IOEG2."},"grove12":{"type":"hy2_4p","standard":"port_uart","note":"UART0 console on signal A (TX, GPIO37) and signal B (RX, GPIO38). The 5V rail is the PM1 CHG_EN output and has no separate software enable."},"grove13":{"type":"hy2_4p","standard":"port_i2c","note":"External I2C on the system bus (SCL GPIO1, SDA GPIO0, 2.2K pull-ups). Signal A is SDA and signal B is SCL; the 5V rail is switched by M5IOE1 IOEG3 and also feeds the I2C level shifter."},"grove14":{"type":"hy2_4p","standard":"port_io","note":"USB1 D+ / D-; do not use as GPIO while USB1 is active. 5V rail switched by M5IOE1 IOEG8."},"grove15":{"type":"hy2_4p","standard":"port_io","note":"Shared with LCD_RST/TP_RST (signal A, GPIO3) and TP_INT (signal B, GPIO2); using this port can reset the panel or lose touch. 5V rail switched by PM1 GPIO2."}}},"m5stamppico":{"schema_version":1,"id":"m5stamppico","name":"M5StampPico","official_name":"M5Stack Stamp-Pico","official_name_verified":true,"legacy_board_id":133,"chip":"esp32_d0wdq6","spec":{"links":{"product":"https://docs.m5stack.com/en/core/Stamp-Pico","schematic":"https://static-cdn.m5stack.com/resource/docs/products/core/stamp_pico/stamp_pico_sch_01.webp","verified":{"product":"datasheet","schematic":"datasheet"}}},"pins":{"0":{"roles":["conn:stamp_right.5"],"verified":{"roles":"datasheet"}},"1":{"roles":["conn:stamp_right.2"],"verified":{"roles":"datasheet"}},"3":{"roles":["conn:stamp_right.3"],"verified":{"roles":"datasheet"}},"18":{"roles":["conn:stamp_left.3"],"verified":{"roles":"datasheet"}},"19":{"roles":["conn:stamp_left.4"],"verified":{"roles":"datasheet"}},"21":{"roles":["bus:internal_i2c.sda","conn:stamp_left.5"],"verified":{"roles":"generated"}},"22":{"roles":["bus:internal_i2c.scl","conn:stamp_left.6"],"verified":{"roles":"generated"}},"25":{"roles":["conn:stamp_left.7"],"verified":{"roles":"datasheet"}},"26":{"roles":["conn:stamp_left.1"],"verified":{"roles":"datasheet"}},"27":{"roles":["dev:rgb_led.data"],"verified":{"roles":"generated"}},"32":{"roles":["conn:port_a.2"],"verified":{"roles":"generated"}},"33":{"roles":["conn:port_a.1"],"verified":{"roles":"generated"}},"36":{"roles":["conn:stamp_left.2"],"verified":{"roles":"datasheet"}}},"buses":{"internal_i2c":{"kind":"i2c","signals":["sda","scl"],"preferred_host":1,"fixed":false,"verified":{"signals":"generated","preferred_host":"generated"}}},"devices":{"rgb_led":{"kind":"led_strip"}},"connectors":{"port_a":{"type":"hy2_4p","standard":"port_i2c","note":"Grove solder footprint shown at the bottom of the official PinMap; the connector may be fitted separately. White signal is GPIO33, yellow signal is GPIO32."},"stamp_left":{"type":"logical_terminals_9","positions":{"8":"pwr:5v","9":"pwr:gnd"},"note":"Positions counted top to bottom in the official component-side PinMap with antenna at the top and Grove pads at the bottom; not schematic connector pin numbers.","verified":{"positions":"datasheet"},"group":"pins"},"stamp_right":{"type":"logical_terminals_6","positions":{"1":"pwr:3v3","4":"chip:en","6":"pwr:gnd"},"note":"Positions counted top to bottom in the official component-side PinMap with antenna at the top and Grove pads at the bottom; not schematic connector pin numbers.","verified":{"positions":"datasheet"},"group":"pins"}}},"m5stamps3":{"schema_version":1,"id":"m5stamps3","name":"M5StampS3","official_name":"M5Stack Stamp-S3","official_name_verified":true,"legacy_board_id":136,"chip":"esp32s3","spec":{"links":{"product":"https://docs.m5stack.com/en/core/Stamp-S3","schematic":"https://m5stack-doc.oss-cn-shenzhen.aliyuncs.com/522/Sch_M5StampS3_v0.2.pdf","verified":{"product":"datasheet","schematic":"datasheet"}}},"pins":{"0":{"roles":["conn:stamp_pads.20"],"verified":{"roles":"datasheet"}},"1":{"roles":["conn:stamp_pads.1"],"verified":{"roles":"datasheet"}},"2":{"roles":["conn:stamp_pads.2"],"verified":{"roles":"datasheet"}},"3":{"roles":["conn:stamp_pads.3"],"verified":{"roles":"datasheet"}},"4":{"roles":["conn:stamp_pads.4"],"verified":{"roles":"datasheet"}},"5":{"roles":["conn:stamp_pads.5"],"verified":{"roles":"datasheet"}},"6":{"roles":["conn:stamp_pads.6"],"verified":{"roles":"datasheet"}},"7":{"roles":["conn:stamp_pads.7"],"verified":{"roles":"datasheet"}},"8":{"roles":["conn:stamp_pads.8"],"verified":{"roles":"datasheet"}},"9":{"roles":["conn:stamp_pads.9"],"verified":{"roles":"datasheet"}},"10":{"roles":["conn:stamp_pads.10"],"verified":{"roles":"datasheet"}},"11":{"roles":["conn:stamp_pads.12"],"verified":{"roles":"datasheet"}},"12":{"roles":["conn:stamp_pads.14"],"verified":{"roles":"datasheet"}},"13":{"roles":["bus:port_a_i2c.sda","conn:port_a.2","conn:stamp_pads.15"],"verified":{"roles":"generated"}},"14":{"roles":["conn:stamp_pads.16"],"verified":{"roles":"datasheet"}},"15":{"roles":["bus:port_a_i2c.scl","conn:port_a.1","conn:stamp_pads.17"],"verified":{"roles":"generated"}},"16":{"roles":["conn:lcd_fpc12.4"],"verified":{"roles":"datasheet"}},"17":{"roles":["conn:lcd_fpc12.3"],"verified":{"roles":"datasheet"}},"18":{"roles":["conn:lcd_fpc12.2"],"verified":{"roles":"datasheet"}},"21":{"roles":["dev:rgb_led.data"],"verified":{"roles":"generated"}},"33":{"roles":["conn:lcd_fpc12.7","conn:lcd_fpc8.3"],"verified":{"roles":"datasheet"}},"34":{"roles":["conn:lcd_fpc12.8","conn:lcd_fpc8.4"],"verified":{"roles":"datasheet"}},"35":{"roles":["conn:lcd_fpc12.9","conn:lcd_fpc8.5"],"verified":{"roles":"datasheet"}},"36":{"roles":["conn:lcd_fpc12.10","conn:lcd_fpc8.6"],"verified":{"roles":"datasheet"}},"37":{"roles":["conn:lcd_fpc12.12","conn:lcd_fpc8.8"],"verified":{"roles":"datasheet"}},"39":{"roles":["conn:stamp_pads.19"],"verified":{"roles":"datasheet"}},"40":{"roles":["conn:stamp_pads.21"],"verified":{"roles":"datasheet"}},"41":{"roles":["conn:stamp_pads.23"],"verified":{"roles":"datasheet"}},"42":{"roles":["conn:stamp_pads.25"],"verified":{"roles":"datasheet"}},"43":{"roles":["conn:stamp_pads.26"],"verified":{"roles":"datasheet"}},"44":{"roles":["conn:stamp_pads.24"],"verified":{"roles":"datasheet"}},"46":{"roles":["conn:stamp_pads.27"],"verified":{"roles":"datasheet"}}},"buses":{"port_a_i2c":{"kind":"i2c","signals":["sda","scl"],"preferred_host":0,"fixed":false,"verified":{"signals":"generated","preferred_host":"generated"}}},"devices":{"rgb_led":{"kind":"led_strip"}},"connectors":{"port_a":{"type":"hy2_4p","standard":"port_i2c","note":"Port A uses GPIO15 (SCL) and GPIO13 (SDA), matching the official PinMap. The bare-module schematic has no HY2.0-4P connector; the product includes a separate HY2.0-4P terminal."},"stamp_pads":{"type":"logical_terminals_28","positions":{"11":"pwr:gnd","13":"pwr:5v","18":"pwr:gnd","22":"chip:en","28":"pwr:3v3"},"note":"Numbers follow M1 in the official v0.2 schematic. Module SMT/DIP pads support different pitch variants; this is an electrical terminal ordering.","verified":{"positions":"datasheet"}},"lcd_fpc12":{"type":"logical_terminals_12","positions":{"1":"pwr:5v","5":"pwr:lcd_bl","6":"pwr:gnd","11":"pwr:3v3"},"note":"Rear J1 12-pin 0.5mm LCD/extension footprint, marked NC in the schematic. Pin 5 BL is the SGM2578 regulated output switched by GPIO38, not a direct GPIO38 connection. Numbers follow J1.","verified":{"positions":"datasheet"}},"lcd_fpc8":{"type":"logical_terminals_8","positions":{"1":"pwr:lcd_bl","2":"pwr:gnd","7":"pwr:3v3"},"note":"Rear J3 8-pin 0.5mm LCD footprint, marked NC in the schematic. Pin 1 BL is the SGM2578 regulated output switched by GPIO38, not a direct GPIO38 connection. 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