deps: patch V8 to support compilation on win-arm64

PR-URL: #47251
Reviewed-By: Yagiz Nizipli <[email protected]>
Reviewed-By: Jiawen Geng <[email protected]>
Reviewed-By: Rafael Gonzaga <[email protected]>
Reviewed-By: Richard Lau <[email protected]>

Author: targos

common.gypi

@@ -36,7 +36,7 @@
 
     # Reset this number to 0 on major V8 upgrades.
     # Increment by one for each non-official patch applied to deps/v8.
-    'v8_embedder_string': '-node.2',
+    'v8_embedder_string': '-node.3',
 
     ##### V8 defaults for Node.js #####
 

deps/v8/src/execution/arm64/simulator-arm64.cc

@@ -34,6 +34,11 @@
 #include "src/trap-handler/trap-handler-simulator.h"
 #endif  // V8_ENABLE_WEBASSEMBLY
 
+#if defined(_MSC_VER)
+// define full memory barrier for msvc
+#define __sync_synchronize _ReadWriteBarrier
+#endif
+
 namespace v8 {
 namespace internal {
 

deps/v8/src/trap-handler/trap-handler-simulator.h

@@ -34,8 +34,10 @@ uintptr_t ProbeMemory(uintptr_t address, uintptr_t pc)
 // "ProbeMemory", but we want something more expressive on stack traces.
 #if V8_OS_DARWIN
     asm("_v8_internal_simulator_ProbeMemory");
-#else
+#elif !defined(_MSC_VER)
     asm("v8_internal_simulator_ProbeMemory");
+#else // MSVC
+    ;
 #endif
 
 }  // namespace v8::internal::trap_handler

deps/v8/test/cctest/test-assembler-arm64.cc

@@ -14771,12 +14771,12 @@ static void AtomicMemoryWHelper(AtomicMemoryLoadSignature* load_funcs,
                                 AtomicMemoryStoreSignature* store_funcs,
                                 uint64_t arg1, uint64_t arg2, uint64_t expected,
                                 uint64_t result_mask) {
-  uint64_t data0[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data1[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data2[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data3[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data4[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data5[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
+  uint64_t data0[2] = {arg2, 0};
+  uint64_t data1[2] = {arg2, 0};
+  uint64_t data2[2] = {arg2, 0};
+  uint64_t data3[2] = {arg2, 0};
+  uint64_t data4[2] = {arg2, 0};
+  uint64_t data5[2] = {arg2, 0};
 
   SETUP();
   SETUP_FEATURE(LSE);
@@ -14838,12 +14838,12 @@ static void AtomicMemoryXHelper(AtomicMemoryLoadSignature* load_funcs,
                                 AtomicMemoryStoreSignature* store_funcs,
                                 uint64_t arg1, uint64_t arg2,
                                 uint64_t expected) {
-  uint64_t data0[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data1[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data2[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data3[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data4[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
-  uint64_t data5[] __attribute__((aligned(kXRegSize * 2))) = {arg2, 0};
+  uint64_t data0[2] = {arg2, 0};
+  uint64_t data1[2] = {arg2, 0};
+  uint64_t data2[2] = {arg2, 0};
+  uint64_t data3[2] = {arg2, 0};
+  uint64_t data4[2] = {arg2, 0};
+  uint64_t data5[2] = {arg2, 0};
 
   SETUP();
   SETUP_FEATURE(LSE);