Merge pull request #684 from pascalgouedo/dd_pgo

CV32E40Pv2 documents and reports updates

Author: pascalgouedo

Project-Descriptions-and-Plans/CV32E40Pv2/Milestone-data/README.md

@@ -1,16 +1,14 @@
-## DRAFT DRAFT DRAFT
-This is **_not_** a final report.  It is here to faciliate reviews.
-
-### TRL-5 Checklists and Reports for the CV32E40P v2
-The OpenHW Group asserts that the documentation, implementation and verification of the CV32E40P v2.0.0 meets the criteria for Technical Readiness Level 5.
+### TRL-5 Reports and Checklist for the CV32E40P v2
+The OpenHW Group asserts that the documentation, implementation and verification of the CV32E40P v1.8.3 meets the criteria for Technical Readiness Level 5.
 The directories and files below this point store the completed checklists, reports (and waivers) in support of this claim.
 
-**RTL_v1.8.0** :
+**RTL_v1.8.3** :
 - README.md : overview summary tables for RTL Freeze results
 - OpenHWGroup_TRL5_for_COREV_RTL_Cheklist-CV32E40P.xls : checklists for the v1.8.0 tag of CV32E40P.
-- CV32E40Pv2_Design_Issue_Summary.xls : summary for total RTL bugs found and resolved.
-- CV32E40Pv2_regression_known_failure.xls : summary for known regression failure (due to tools/set-up limitation).
-- CV32E40Pv2_uncovered_coverage_explanation.xls : summary for any remaining coverage holes.
-- CV32E40Pv2_waiver_list.xls : summary for the waivers applied to RTL Code Coverage and/or Functional Coverage.
-- Reports : RTL Code Coverage, Functional coverage, Formal, RISCOF and Simulation Regression reports in support of RTL Freeze.
-  - index.html : start from this file. It presents all quick links to directly jump to information.
+- CV32E40Pv2_Design_Issue_Summary.xls : List of all Documentation and RTL issues found and resolved.
+- CV32E40Pv2_not_verified_features.xls : List of features not verified.
+- CV32E40Pv2_regression_known_failure.xls : Summary of known non-regression failures.
+- CV32E40Pv2_uncovered_coverage_explanation.xls : Summary for any remaining RTL code coverage holes.
+- CV32E40Pv2_waiver_list.xls : Summary of the waivers applied to RTL Code Coverage and/or Functional Coverage.
+- index.html : Central html file describing and pointing to all Verififcation documents and reports.
+- Reports : RTL Code Coverage, Functional coverage, RISC-V ISA Formal Coverage, riscvISACOV Coverage, RISCOF and Simulation Regression reports in support of RTL Freeze.

Project-Descriptions-and-Plans/CV32E40Pv2/Milestone-data/RTL_v1.8.3/CV32E40Pv2_not_verified_features.xlsx

@@ -1,25 +1,25 @@
-## RTL_v1.8.3_summary
+## RTL_v1.8.3 summary
 Short summary table for the RTL_v1.8.3 results overview
 
 ### Formal Verification
-Control and Datapath assertions checking runs launched on 3 configurations  
-*430 assertions. (TODO:update the number of assertions)*
-| Configurations                          | Status                                           |
------------------------------------------ | ------------------------------------------------ |
-PULP                                      | Successful unbounded check (11 days)             |
-PULP_FPU (0 cycle latency)                | still running after 18 days. No error so far.    |
-PULP_FPU_ZFINX_2CYCLAT (2 cycles latency) | still running after 18 days. No error so far.    |
+Control and Datapath assertions checking runs launched on 2 configurations with 198 assertions globally.
+| Configurations  | Status                                                     |
+------------------| -------------------------- |
+PULP              | Successful unbounded check |
+PULP_FPU_0CYCLAT  | Successful unbounded check |
 
 ### Regression Results
 *Some testcases run multiple seeds in one regression*
 |Configurations             | xplup      || F + xpulp  || F + xpulp (lat. 1) || F + xpulp (lat. 2) || Xpulp + Zfinx || Xpulp + Zfinx (lat 1) || Xpulp + Zfinx (lat. 2) || **Total All Cfg**  ||
 ----------------------------|------|------|------|------|------|--------------|------|--------------|------|---------|-------|----------------|------|------------------|----------|----------|
 **Regress File**            | Pass | Fail | Pass | Fail | Pass | Fail         | Pass | Fail         | Pass | Fail    | Pass  | Fail           | Pass | Fail             | **Pass** | **Fail** |
 cv32e40pv2_fpu_instr        | NA   | NA   | 1504 | 0    | 1504 | 0            | 1504 | 0            | 1504 | 0       | 1504  | 0              | 1504 | 0                | 9024     | 0        |
-cv32e40pv2_interrupt_debug	| 1701 | 0    | 1950 | 2    | 1951 | 1            | 1951 | 1            | 1951 | 1       | 1952  | 0              | 1949 | 3                | 13405    | 8        |
+cv32e40pv2_interrupt_debug	| 1701 | 0    | 1951 | 0    | 1950 | 1            | 1951 | 1            | 1952 | 0       | 1952  | 0              | 1951 | 1                | 13408    | 3        |
 cv32e40pv2_xpulp_instr      | 1433 | 0    | 1433 | 0    | 1433 | 0            | 1433 | 0            | 1433 | 0       | 1433  | 0              | 1433 | 0                | 10031    | 0        |
 cv32e40pv2_legacy_v1        | 29   | 0    | 29   | 0    | 29   | 0            | 29   | 0            | 29   | 0       | 29    | 0              | 29   | 0                | 203      | 0        |
-**Total number of tests**   | 3134 | 0    | 4887 | 2    | 4888 | 1            | 4888 | 1            | 4888 | 1       | 4889  | 0              | 4886 | 3                | 32663    | 8        |
+**Total number of tests**   | 3134 | 0    | 4888 | 0    | 4887 | 1            | 4888 | 1            | 4889 | 0       | 4889  | 0              | 4888 | 1                | 32666    | 3        |
+
+The 3 failing tests are going in time-out. Generally they just require much longer time-out setup to successfully run but which can not be applied systematically on all tests.
 
 ### Riscof Architecture Test
 | Configurations               | Status |
@@ -30,8 +30,7 @@ PULP_FPU_1CYCLAT configuration | Pass   |
 PULP_FPU_2CYCLAT configuration | Pass   |
 
 ### RTL Code Coverage
-*Only left with holes in cv32e40p_controller (6 causes resulting in 17 holes).
-Seeking help from Openhwgroup community*
+*Still some holes in cv32e40p_controller (2 causes resulting in 16 holes).
 | Configurations               | Statement | Branch | Condition | 
 -------------------------------|-----------|--------|-----------|
 PULP Configuration             | 99.8%     | 99.6%  | 99.2%     | 
@@ -47,7 +46,7 @@ Debug                  | 100%                                                 |
 Interrupts             | 100%                                                 |
 OBI                    | 100%                                                 |
 Assertions & Directive | 100%                                                 |
-riscvISACOV            | 95.01% (*optional. We use Formal OneSpin tool to verify instructions.*)|
+riscvISACOV            | 95.08% (*optional. We use Siemens Questa Processor tool to verify instructions.*)|
 
 (2) **Combined from 3 ZFINX configurations** using PULP_ZFINX_0CYCLAT as master
 | Covergroups          | Status                                               |