x86/cpufeatures: Add CPUID_8C86_0000_EDX CPUID leaf

hygon inclusion
category: feature
CVE: NA

---------------------------

This is a pure feature bits leaf. Add SM3 and SM4 feature bits from
this leaf on Hygon CPUs.

Signed-off-by: hanliyang <hanliyang@hygon.cn>
[disabled-features.h and required-features.h removed by the commit
commit 8f97566
Author: Xin Li (Intel) <xin@zytor.com>
Date:   Mon Mar 10 08:32:12 2025 +0100

    x86/cpufeatures: Remove {disabled,required}-features.h

    The functionalities of {disabled,required}-features.h have been replaced with
    the auto-generated generated/<asm/cpufeaturemasks.h> header.

    Thus they are no longer needed and can be removed.

    None of the macros defined in {disabled,required}-features.h is used in tools,
    delete them too.

    Signed-off-by: Xin Li (Intel) <xin@zytor.com>
    Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Link: https://lore.kernel.org/r/20250305184725.3341760-4-xin@zytor.com]
Link: deepin-community#350
(cherry picked from commit 4a0be8d)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>

Conflicts:
	arch/x86/include/asm/cpufeature.h
	arch/x86/include/asm/cpufeatures.h
	arch/x86/include/asm/disabled-features.h
	arch/x86/include/asm/required-features.h

Author: hanliyang

arch/x86/include/asm/cpufeature.h

@@ -35,6 +35,8 @@ enum cpuid_leafs
 	CPUID_8000_001F_EAX,
 	CPUID_8000_0021_EAX,
 	CPUID_LNX_5,
+	CPUID_C000_0006_EAX,
+	CPUID_8C86_0000_EDX,	/* 23 */
 	NR_CPUID_WORDS,
 };
 

arch/x86/include/asm/cpufeatures.h

@@ -5,7 +5,7 @@
 /*
  * Defines x86 CPU feature bits
  */
-#define NCAPINTS			22	   /* N 32-bit words worth of info */
+#define NCAPINTS			24	   /* N 32-bit words worth of info */
 #define NBUGINTS			2	   /* N 32-bit bug flags */
 
 /*
@@ -519,6 +519,10 @@
 #define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */
 #define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */
 
+/* HYGON-defined CPU features, CPUID level 0x8c860000:0 (EDX), word 23 */
+#define X86_FEATURE_SM3			(23*32 + 1) /* SM3 instructions */
+#define X86_FEATURE_SM4			(23*32 + 2) /* SM4 instructions */
+
 /*
  * BUG word(s)
  */

arch/x86/kernel/cpu/hygon.c

@@ -122,6 +122,18 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c)
 	resctrl_cpu_detect(c);
 }
 
+static void init_hygon_cap(struct cpuinfo_x86 *c)
+{
+	/* Test for Extended Feature Flags presence */
+	if (cpuid_eax(0x8C860000) >= 0x8C860000) {
+		/*
+		 * Store Extended Feature Flags of the CPU capability
+		 * bit array
+		 */
+		c->x86_capability[CPUID_8C86_0000_EDX] = cpuid_edx(0x8C860000);
+	}
+}
+
 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
 {
 	u64 msr;
@@ -278,6 +290,8 @@ static void init_hygon(struct cpuinfo_x86 *c)
 
 	/* Hygon CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
 	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
+
+	init_hygon_cap(c);
 }
 
 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)