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Support SPARC and SPARC64
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‎.github/.cspell/project-dictionary.txt‎

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@@ -49,6 +49,7 @@ lwarx
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lwsync
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machdep
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mcpu
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membar
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memd
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memw
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mfcr

‎.github/workflows/ci.yml‎

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@@ -234,6 +234,11 @@ jobs:
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target: s390x-unknown-linux-gnu
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- rust: nightly
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target: s390x-unknown-linux-gnu
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# TODO: https://github.com/rust-lang/rust/pull/132472
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# - rust: nightly-2024-1?-?? # Rust 1.8?, LLVM 19 (oldest version we can use asm_experimental_arch on this target)
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# target: sparc64-unknown-linux-gnu
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# - rust: nightly
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# target: sparc64-unknown-linux-gnu
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- rust: '1.59' # LLVM 13
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target: thumbv7neon-unknown-linux-gnueabihf
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- rust: '1.74' # LLVM 17 (oldest version that MaybeUninit register is supported)

‎README.md‎

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@@ -18,7 +18,7 @@ This crate provides a way to soundly perform such operations.
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## Platform Support
2020

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Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, PowerPC, s390x, MSP430, Arm64EC, AVR, Hexagon, M68k, and Xtensa are supported.
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Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, PowerPC, s390x, MSP430, Arm64EC, AVR, SPARC, Hexagon, M68k, and Xtensa are supported.
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| target_arch | primitives | load/store | swap/CAS |
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| -------------------------------- | --------------------------------------------------- |:----------:|:--------:|
@@ -40,6 +40,8 @@ Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, Power
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| arm64ec \[4] | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128 | ✓ | ✓ |
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| msp430 \[4] (experimental) | isize,usize,i8,u8,i16,u16 | ✓ | ✓ |
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| avr \[4] (experimental) | isize,usize,i8,u8,i16,u16 | ✓ | ✓ |
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| sparc \[4] \[7] (experimental) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓ |
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| sparc64 \[4] (experimental) | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
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| hexagon \[4] (experimental) | isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 | ✓ | ✓ |
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| m68k \[4] (experimental) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓\[1] |
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| xtensa \[4] (experimental) | isize,usize,i8,u8,i16,u16,i32,u32 | ✓ | ✓\[1] |
@@ -50,6 +52,7 @@ Currently, x86, x86_64, Arm, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, Power
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\[4] Requires nightly due to `#![feature(asm_experimental_arch)]`.<br>
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\[5] Requires cmpxchg16b target feature (enabled by default on Apple and Windows (except Windows 7) targets).<br>
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\[6] Requires target-cpu pwr8+ (powerpc64le is pwr8 by default).<br>
55+
\[7] Requires CAS instruction support.<br>
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Feel free to submit an issue if your target is not supported yet.
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‎build.rs‎

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@@ -41,7 +41,7 @@ fn main() {
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// TODO: handle multi-line target_feature_fallback
4242
// grep -F 'target_feature_fallback("' build.rs | grep -Ev '^ *//' | sed -E 's/^.*target_feature_fallback\(//; s/",.*$/"/' | LC_ALL=C sort -u | tr '\n' ',' | sed -E 's/,$/\n/'
4343
println!(
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r#"cargo:rustc-check-cfg=cfg(atomic_maybe_uninit_target_feature,values("a","cmpxchg16b","fast-serialization","isa-68020","lse","lse128","lse2","mclass","partword-atomics","quadword-atomics","rcpc","rcpc3","v5te","v6","v7","v8","v8m","x87","zaamo","zabha"))"#
44+
r#"cargo:rustc-check-cfg=cfg(atomic_maybe_uninit_target_feature,values("a","cmpxchg16b","fast-serialization","hasleoncasa","isa-68020","lse","lse128","lse2","mclass","partword-atomics","quadword-atomics","rcpc","rcpc3","v5te","v6","v7","v8","v8m","v9","x87","zaamo","zabha"))"#
4545
);
4646
}
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@@ -107,6 +107,15 @@ fn main() {
107107
println!("cargo:rustc-cfg=atomic_maybe_uninit_unstable_asm_experimental_arch");
108108
}
109109
}
110+
"sparc" | "sparc64" => {
111+
// TODO: https://github.com/rust-lang/rust/pull/132472
112+
// if version.nightly
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// && version.probe(84, 2024, 1?, ?)
114+
// && is_allowed_feature("asm_experimental_arch")
115+
// {
116+
println!("cargo:rustc-cfg=atomic_maybe_uninit_unstable_asm_experimental_arch");
117+
// }
118+
}
110119
_ => {}
111120
}
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@@ -351,6 +360,29 @@ fn main() {
351360
// bcr 14,0
352361
target_feature_fallback("fast-serialization", arch9_features);
353362
}
363+
"sparc" => {
364+
let mut hasleoncasa = false;
365+
// https://github.com/llvm/llvm-project/pull/109278
366+
// https://github.com/rust-lang/rust/blob/1.82.0/compiler/rustc_target/src/spec/targets/sparc_unknown_linux_gnu.rs#L17
367+
let mut v9 = target_os == "linux" || target_os == "solaris";
368+
if let Some(cpu) = target_cpu() {
369+
// https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Sparc/Sparc.td
370+
match &*cpu {
371+
"myriad2" | "myriad2.1" | "myriad2.2" | "myriad2.3" | "ma2100" | "ma2150"
372+
| "ma2155" | "ma2450" | "ma2455" | "ma2x5x" | "ma2080" | "ma2085"
373+
| "ma2480" | "ma2485" | "ma2x8x" | "gr712rc" | "leon4" | "gr740" => {
374+
hasleoncasa = true;
375+
}
376+
"v9" | "ultrasparc" | "ultrasparc3" | "niagara" | "niagara2" | "niagara3"
377+
| "niagara4" => v9 = true,
378+
_ => v9 = false,
379+
}
380+
}
381+
// As of rustc 1.80, target_feature "hasleoncasa"/"v9" is not available on rustc side:
382+
// https://github.com/rust-lang/rust/blob/1.80.0/compiler/rustc_target/src/target_features.rs
383+
target_feature_fallback("hasleoncasa", hasleoncasa);
384+
target_feature_fallback("v9", v9);
385+
}
354386
"m68k" => {
355387
// https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/M68k/M68k.td
356388
// Linux requires M68020+.

‎src/arch/cfgs/sparc.rs‎

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@@ -0,0 +1,66 @@
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// SPDX-License-Identifier: Apache-2.0 OR MIT
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3+
#![allow(missing_docs)]
4+
5+
#[macro_export]
6+
macro_rules! cfg_has_atomic_8 {
7+
($($tt:tt)*) => { $($tt)* };
8+
}
9+
#[macro_export]
10+
macro_rules! cfg_no_atomic_8 {
11+
($($tt:tt)*) => {};
12+
}
13+
#[macro_export]
14+
macro_rules! cfg_has_atomic_16 {
15+
($($tt:tt)*) => { $($tt)* };
16+
}
17+
#[macro_export]
18+
macro_rules! cfg_no_atomic_16 {
19+
($($tt:tt)*) => {};
20+
}
21+
#[macro_export]
22+
macro_rules! cfg_has_atomic_32 {
23+
($($tt:tt)*) => { $($tt)* };
24+
}
25+
#[macro_export]
26+
macro_rules! cfg_no_atomic_32 {
27+
($($tt:tt)*) => {};
28+
}
29+
// TODO: V8+ with 64-bit g/o reg
30+
#[cfg(target_arch = "sparc")]
31+
#[macro_export]
32+
macro_rules! cfg_has_atomic_64 {
33+
($($tt:tt)*) => {};
34+
}
35+
// TODO: V8+ with 64-bit g/o reg
36+
#[cfg(target_arch = "sparc")]
37+
#[macro_export]
38+
macro_rules! cfg_no_atomic_64 {
39+
($($tt:tt)*) => { $($tt)* };
40+
}
41+
#[cfg(target_arch = "sparc64")]
42+
#[macro_export]
43+
macro_rules! cfg_has_atomic_64 {
44+
($($tt:tt)*) => { $($tt)* };
45+
}
46+
#[cfg(target_arch = "sparc64")]
47+
#[macro_export]
48+
macro_rules! cfg_no_atomic_64 {
49+
($($tt:tt)*) => {};
50+
}
51+
#[macro_export]
52+
macro_rules! cfg_has_atomic_128 {
53+
($($tt:tt)*) => {};
54+
}
55+
#[macro_export]
56+
macro_rules! cfg_no_atomic_128 {
57+
($($tt:tt)*) => { $($tt)* };
58+
}
59+
#[macro_export]
60+
macro_rules! cfg_has_atomic_cas {
61+
($($tt:tt)*) => { $($tt)* };
62+
}
63+
#[macro_export]
64+
macro_rules! cfg_no_atomic_cas {
65+
($($tt:tt)*) => {};
66+
}

‎src/arch/mod.rs‎

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@@ -39,6 +39,16 @@
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target_arch = "powerpc",
4040
target_arch = "powerpc64",
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target_arch = "s390x",
42+
all(
43+
target_arch = "sparc",
44+
any(
45+
target_feature = "hasleoncasa",
46+
atomic_maybe_uninit_target_feature = "hasleoncasa",
47+
target_feature = "v9",
48+
atomic_maybe_uninit_target_feature = "v9",
49+
),
50+
),
51+
target_arch = "sparc64",
4252
target_arch = "xtensa",
4353
),
4454
atomic_maybe_uninit_unstable_asm_experimental_arch,
@@ -108,6 +118,20 @@ mod riscv;
108118
#[cfg(atomic_maybe_uninit_unstable_asm_experimental_arch)]
109119
#[cfg_attr(atomic_maybe_uninit_s390x_no_reg_addr, path = "s390x_no_reg_addr.rs")]
110120
mod s390x;
121+
#[cfg(any(
122+
all(
123+
target_arch = "sparc",
124+
any(
125+
target_feature = "hasleoncasa",
126+
atomic_maybe_uninit_target_feature = "hasleoncasa",
127+
target_feature = "v9",
128+
atomic_maybe_uninit_target_feature = "v9",
129+
),
130+
),
131+
target_arch = "sparc64",
132+
))]
133+
#[cfg(atomic_maybe_uninit_unstable_asm_experimental_arch)]
134+
mod sparc;
111135
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
112136
mod x86;
113137
#[cfg(target_arch = "xtensa")]

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