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thejpsterthejpster
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Adds ARMv6 targets.
Targets added in rust-lang/rust#150138. Tested with local build of rustc. Will fail with the versions of nightly rust specified in the CI config. Need to wait for 2025-01-26 to come out.
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43 files changed

Lines changed: 1046 additions & 12 deletions

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‎.cargo/config.toml‎

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@@ -34,6 +34,15 @@ runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nogr
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[target.thumbv7a-none-eabi]
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runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
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[target.armv6-none-eabihf]
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runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
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[target.armv6-none-eabi]
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runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
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[target.thumbv6-none-eabi]
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runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
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[target.armv5te-none-eabi]
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runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
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‎aarch32-cpu/src/register/cpsr.rs‎

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@@ -75,7 +75,11 @@ impl Cpsr {
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/// `thumb*` targets, as Thumb-1 cannot do an MRS.
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#[cfg_attr(not(feature = "check-asm"), inline)]
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#[cfg_attr(
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any(arm_architecture = "v4t", arm_architecture = "v5te"),
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any(
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arm_architecture = "v4t",
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arm_architecture = "v5te",
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arm_architecture = "v6"
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),
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instruction_set(arm::a32)
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)]
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pub fn read() -> Self {
@@ -108,7 +112,11 @@ impl Cpsr {
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/// `thumb*` targets, as Thumb-1 cannot do an MSR.
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#[cfg_attr(not(feature = "check-asm"), inline)]
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#[cfg_attr(
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any(arm_architecture = "v4t", arm_architecture = "v5te"),
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any(
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arm_architecture = "v4t",
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arm_architecture = "v5te",
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arm_architecture = "v6"
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),
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instruction_set(arm::a32)
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)]
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pub unsafe fn write(_value: Self) {

‎aarch32-cpu/src/register/mod.rs‎

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Original file line numberDiff line numberDiff line change
@@ -225,7 +225,11 @@ pub trait SysRegRead: SysReg {
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/// may have side-effects.
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#[cfg_attr(not(feature = "check-asm"), inline)]
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#[cfg_attr(
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any(arm_architecture = "v4t", arm_architecture = "v5te"),
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any(
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arm_architecture = "v4t",
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arm_architecture = "v5te",
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arm_architecture = "v6"
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),
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instruction_set(arm::a32)
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)]
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unsafe fn read_raw() -> u32 {
@@ -261,7 +265,11 @@ pub trait SysRegWrite: SysReg {
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/// writing valid data here.
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#[cfg_attr(not(feature = "check-asm"), inline)]
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#[cfg_attr(
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any(arm_architecture = "v4t", arm_architecture = "v5te"),
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any(
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arm_architecture = "v4t",
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arm_architecture = "v5te",
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arm_architecture = "v6"
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),
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instruction_set(arm::a32)
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)]
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unsafe fn write_raw(_value: u32) {

‎arm-targets/src/lib.rs‎

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Original file line numberDiff line numberDiff line change
@@ -227,7 +227,10 @@ impl Arch {
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Some(Arch::Armv7A)
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} else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") {
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Some(Arch::Armv8A)
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} else if target.starts_with("arm-") {
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} else if target.starts_with("arm-")
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|| target.starts_with("armv6-")
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|| target.starts_with("thumbv6-")
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{
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// If not specified, assume Armv6
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Some(Arch::Armv6)
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} else {
@@ -407,6 +410,26 @@ mod test {
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assert_eq!(target_info.abi(), Some(Abi::Eabi));
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}
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#[test]
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fn armv6_none_eabi() {
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let target = "armv6-none-eabi";
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let target_info = process_target(target);
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assert_eq!(target_info.isa(), Some(Isa::A32));
418+
assert_eq!(target_info.arch(), Some(Arch::Armv6));
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assert_eq!(target_info.profile(), Some(Profile::Legacy));
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assert_eq!(target_info.abi(), Some(Abi::Eabi));
421+
}
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#[test]
424+
fn armv6_none_eabihf() {
425+
let target = "armv6-none-eabihf";
426+
let target_info = process_target(target);
427+
assert_eq!(target_info.isa(), Some(Isa::A32));
428+
assert_eq!(target_info.arch(), Some(Arch::Armv6));
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assert_eq!(target_info.profile(), Some(Profile::Legacy));
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assert_eq!(target_info.abi(), Some(Abi::EabiHf));
431+
}
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410433
#[test]
411434
fn arm_unknown_linux_gnueabi() {
412435
let target = "arm-unknown-linux-gnueabi";

‎examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out‎

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@@ -0,0 +1,14 @@
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Hello, this is an data abort exception example
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data abort occurred
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DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
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DFSR Status: Ok(AlignmentFault)
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caught unaligned_from_a32
6+
caught fault on COUNTER
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Doing it again
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data abort occurred
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DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_a32
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caught fault on COUNTER
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Skipping instruction
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Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out‎

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@@ -0,0 +1,14 @@
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Hello, this is an data abort exception example
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data abort occurred
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DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
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DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_a32
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caught fault on COUNTER
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Doing it again
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data abort occurred
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DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_a32
12+
caught fault on COUNTER
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Skipping instruction
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Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-a32-thumbv6-none-eabi.out‎

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Hello, this is an data abort exception example
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data abort occurred
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DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_a32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_a32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out‎

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@@ -0,0 +1,14 @@
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Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_t32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_t32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_t32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_t32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

‎examples/versatileab/reference/abt-exception-t32-thumbv6-none-eabi.out‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Hello, this is an data abort exception example
2+
data abort occurred
3+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
4+
DFSR Status: Ok(AlignmentFault)
5+
caught unaligned_from_t32
6+
caught fault on COUNTER
7+
Doing it again
8+
data abort occurred
9+
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
10+
DFSR Status: Ok(AlignmentFault)
11+
caught unaligned_from_t32
12+
caught fault on COUNTER
13+
Skipping instruction
14+
Recovered from fault OK!

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