add scpsys driver

Documentation/devicetree/bindings/power/mediatek,power-controller.yaml

@@ -23,6 +23,7 @@ properties:
 
   compatible:
     enum:
+      - mediatek,mt6589-power-controller
       - mediatek,mt6735-power-controller
       - mediatek,mt6795-power-controller
       - mediatek,mt6893-power-controller

arch/arm/boot/dts/mediatek/mt6589.dtsi

@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/mt6589-clk.h>
 #include <dt-bindings/pinctrl/mt6589-pinfunc.h>
+#include <dt-bindings/power/mt6589-power.h>
 
 / {
 	#address-cells = <1>;
@@ -113,6 +114,73 @@
 			#reset-cells = <1>;
 		};
 
+		scpsys: syscon@10006000 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0x10006000 0x1000>;
+			#power-domain-cells = <1>;
+
+			spm: power-controller {
+				compatible = "mediatek,mt6589-power-controller";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#power-domain-cells = <1>;
+
+				power-domain@MT6589_POWER_DOMAIN_MD1 {
+					reg = <MT6589_POWER_DOMAIN_MD1>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_MD2 {
+					reg = <MT6589_POWER_DOMAIN_MD2>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_DPY {
+					reg = <MT6589_POWER_DOMAIN_DPY>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_DIS {
+					reg = <MT6589_POWER_DOMAIN_DIS>;
+					clocks = <&topckgen CLK_TOP_MUX_DISP>;
+					clock-names = "disp";
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_MFG {
+					reg = <MT6589_POWER_DOMAIN_MFG>;
+					clocks = <&topckgen CLK_TOP_MUX_MFG>,
+						 <&topckgen CLK_TOP_MUX_SMI_MFG_AS>;
+					clock-names = "mfg", "mfg_as";
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_ISP {
+					reg = <MT6589_POWER_DOMAIN_ISP>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_IFR {
+					reg = <MT6589_POWER_DOMAIN_IFR>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_VEN {
+					reg = <MT6589_POWER_DOMAIN_VEN>;
+					clocks = <&topckgen CLK_TOP_MUX_VENC>;
+					clock-names = "venc";
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT6589_POWER_DOMAIN_VDE {
+					reg = <MT6589_POWER_DOMAIN_VDE>;
+					clocks = <&topckgen CLK_TOP_MUX_VDEC>;
+					clock-names = "vdec";
+					#power-domain-cells = <0>;
+				};
+			};
+		};
+
 		mfgsys: syscon@10206000 {
 			compatible = "mediatek,mt6589-mfgsys", "syscon";
 			reg = <0x10206000 0x1000>;

arch/arm/configs/lenovo-blade_defconfig

@@ -119,6 +119,9 @@ CONFIG_BMC150_MAGN_I2C=y
 ## Reset
 #CONFIG_RESET_CONTROLLER
 
+## Power Management
+CONFIG_MTK_SCPSYS_PM_DOMAINS=y
+
 ## Battery
 
 ## Regulator

drivers/pmdomain/mediatek/mt6589-pm-domains.h

@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT6589_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT6589_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mt6589-power.h>
+
+/*
+ * MT6589 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt6589[] = {
+	[MT6589_POWER_DOMAIN_MD1] = {
+		.name = "md1",
+		.sta_mask = PWR_STATUS_MD1,
+		.ctl_offs = SPM_MD1_PWR_CON,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = 0, /* don't have */
+		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+		/*
+		.bp_cfg = {
+			BUS_PROT_INFRA_UPDATE_TOPAXI(MT6589_TOP_AXI_PROT_EN_MD1),
+		},
+		*/
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_MD2] = {
+		.name = "md2",
+		.sta_mask = PWR_STATUS_CONN,
+		.ctl_offs = SPM_CONN_PWR_CON,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = 0, /* don't have */
+		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+		/*
+		.bp_cfg = {
+			BUS_PROT_INFRA_UPDATE_TOPAXI(MT6589_TOP_AXI_PROT_EN_MD2),
+		},
+		*/
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_DPY] = {
+		.name = "dpy",
+		.sta_mask = PWR_STATUS_DDRPHY,
+		.ctl_offs = 0x0240,
+		.caps = MTK_SCPD_ALWAYS_ON | MTK_SCPD_NO_SRAM,
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_DIS] = {
+		.name = "dis",
+		.sta_mask = PWR_STATUS_DISP,
+		.ctl_offs = SPM_DIS_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		/*
+		.bp_cfg = {
+			BUS_PROT_INFRA_UPDATE_TOPAXI(MT6589_TOP_AXI_PROT_EN_DIS),
+		},
+		*/
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_MFG] = {
+		.name = "mfg",
+		.sta_mask = PWR_STATUS_MFG,
+		.ctl_offs = SPM_MFG_PWR_CON,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+		/*
+		.bp_cfg = {
+			BUS_PROT_INFRA_UPDATE_TOPAXI(TODO),
+		},
+		*/
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_ISP] = {
+		.name = "isp",
+		.sta_mask = PWR_STATUS_ISP,
+		.ctl_offs = SPM_ISP_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+		/*
+		.bp_cfg = BUS_PROT_INFRA_UPDATE_TOPAXI(TODO), img_s_prot_en?,
+		*/
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_IFR] = {
+		.name = "ifr",
+		.sta_mask = PWR_STATUS_INFRASYS,
+		.ctl_offs = 0x0234,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.caps = MTK_SCPD_ALWAYS_ON,
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_VEN] = {
+		.name = "ven",
+		.sta_mask = BIT(7),
+		.ctl_offs = SPM_VEN_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+	[MT6589_POWER_DOMAIN_VDE] = {
+		.name = "vde",
+		.sta_mask = BIT(8),
+		.ctl_offs = SPM_VDE_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+		.pwr_sta_offs = SPM_PWR_STATUS,
+		.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
+	},
+};
+
+static const struct scpsys_soc_data mt6589_scpsys_data = {
+	.domains_data = scpsys_domain_data_mt6589,
+	.num_domains = ARRAY_SIZE(scpsys_domain_data_mt6589),
+};
+
+#endif /* __SOC_MEDIATEK_MT6589_PM_DOMAINS_H */

drivers/pmdomain/mediatek/mtk-pm-domains.c

@@ -16,6 +16,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/soc/mediatek/infracfg.h>
 
+#include "mt6589-pm-domains.h"
 #include "mt6735-pm-domains.h"
 #include "mt6795-pm-domains.h"
 #include "mt6893-pm-domains.h"
@@ -277,9 +278,11 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
 			goto err_pwr_ack;
 	}
 
-	ret = scpsys_sram_enable(pd);
-	if (ret < 0)
-		goto err_disable_subsys_clks;
+	if (!MTK_SCPD_CAPS(pd, MTK_SCPD_NO_SRAM)) {
+		ret = scpsys_sram_enable(pd);
+		if (ret < 0)
+			goto err_disable_subsys_clks;
+	}
 
 	ret = scpsys_bus_protect_disable(pd);
 	if (ret < 0)
@@ -297,7 +300,8 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
 err_enable_bus_protect:
 	scpsys_bus_protect_enable(pd);
 err_disable_sram:
-	scpsys_sram_disable(pd);
+	if (!MTK_SCPD_CAPS(pd, MTK_SCPD_NO_SRAM))
+		scpsys_sram_disable(pd);
 err_disable_subsys_clks:
 	if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION))
 		clk_bulk_disable_unprepare(pd->num_subsys_clks,
@@ -320,9 +324,11 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
 	if (ret < 0)
 		return ret;
 
-	ret = scpsys_sram_disable(pd);
-	if (ret < 0)
-		return ret;
+	if (!MTK_SCPD_CAPS(pd, MTK_SCPD_NO_SRAM)) {
+		ret = scpsys_sram_disable(pd);
+		if (ret < 0)
+			return ret;
+	}
 
 	if (pd->data->ext_buck_iso_offs && MTK_SCPD_CAPS(pd, MTK_SCPD_EXT_BUCK_ISO))
 		regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs,
@@ -616,6 +622,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
 }
 
 static const struct of_device_id scpsys_of_match[] = {
+	{
+		.compatible = "mediatek,mt6589-power-controller",
+		.data = &mt6589_scpsys_data,
+	},
 	{
 		.compatible = "mediatek,mt6735-power-controller",
 		.data = &mt6735_scpsys_data,

drivers/pmdomain/mediatek/mtk-pm-domains.h

@@ -13,6 +13,7 @@
 #define MTK_SCPD_EXT_BUCK_ISO		BIT(6)
 #define MTK_SCPD_HAS_INFRA_NAO		BIT(7)
 #define MTK_SCPD_STRICT_BUS_PROTECTION	BIT(8)
+#define MTK_SCPD_NO_SRAM		BIT(10)
 #define MTK_SCPD_CAPS(_scpd, _x)	((_scpd)->data->caps & (_x))
 
 #define SPM_VDE_PWR_CON			0x0210
@@ -33,9 +34,11 @@
 
 #define PWR_STATUS_MD1			BIT(0)
 #define PWR_STATUS_CONN			BIT(1)
+#define PWR_STATUS_DDRPHY		BIT(2)
 #define PWR_STATUS_DISP			BIT(3)
 #define PWR_STATUS_MFG			BIT(4)
 #define PWR_STATUS_ISP			BIT(5)
+#define PWR_STATUS_INFRASYS		BIT(6)
 #define PWR_STATUS_VDEC			BIT(7)
 #define PWR_STATUS_VENC_LT		BIT(20)
 #define PWR_STATUS_VENC			BIT(21)

include/dt-bindings/power/mt6589-power.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_MT6589_POWER_H
+#define _DT_BINDINGS_POWER_MT6589_POWER_H
+
+#define MT6589_POWER_DOMAIN_MD1	0
+#define MT6589_POWER_DOMAIN_MD2	1
+#define MT6589_POWER_DOMAIN_DPY	2
+#define MT6589_POWER_DOMAIN_DIS	3
+#define MT6589_POWER_DOMAIN_MFG	4
+#define MT6589_POWER_DOMAIN_ISP	5
+#define MT6589_POWER_DOMAIN_IFR	6
+#define MT6589_POWER_DOMAIN_VEN	7
+#define MT6589_POWER_DOMAIN_VDE	8
+
+#endif /* _DT_BINDINGS_POWER_MT6589_POWER_H */