v3.0.1

Added missing header files to BDDISASM_PUBLIC_HEADERS.

v3.0.0

• Implemented support for minimal decoding: integrators can choose to use the new API which returns a smaller structure (64-bytes); instruction metadata can be retrieved using new API functions
• Improved decoding performance by performing instruction validity checks during decode tree lookup
• Multiple improvements & fixes around APX & REX2 instructions
• Re-worked the ISA generator library

v2.2.0

Multiple improvements & fixes. Consult the CHANGELOG for more information.

v2.1.5

Fixed UBSan warnings + some other warnings.

v2.1.4

• Removed no longer needed static assert, that caused build errors.

v2.1.3

• Aligned BDDISASM APX instructions syntax with some of the Intel recommendations (using the suffix notation for NF and ZU indications, using finite set notation for DFV operands).
• The ZU indication is appended as a mnemonic suffix, as per recomandations. However, in case of SETcc instructions, BDDISASM will append the ZU indication AFTER the condition code (similar to CMPccXADD and with initial SETcc.ZU specification).
• The DFV (default flags value) operand obeys the finite set notation, but it is placed as the last operand of the instruction.
• Added Read access for the rIP operand for the SYSCALL instruction.
• Added SCS, rCX, rDX operands for the SYSEXIT instruction.
• Added Read access for the rIP operand for some CALL instructions.

v2.1.0

Added support in BDDISASM for multiple new Intel extensions: REX2, APX, USERMSR.
Added support in BDSHEMU for some REX2 and APX instructions.
Added support in BDSHEMU for loop tracking & direct shellcode emulation.
Reduced the size of the INSTRUX structure, and improved decoding performance.
New decoding option allow to skip implicit operands from being decoded.
Re-worked the Python isagenerator scripts.
More info about the changes in this version can be consulted in the CHANGELOG.

v1.37.0

Added support for Intel AMX-COMPLEX instructions.
Added support for AMD RMPQUERY instruction.
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
Improved comments & improved vector length specifiers.

v1.34.10

• Switched to internally defined types.
• WRUSSD and WRUSSQ cannot be executed when CPL != 0.
• Fixed High8 handling in NdGetFullAccessMap.
• Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed...

v1.34.7

Support for RDTSC in bdshemu.
Implemented a reverse operand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup.
Moved helper functions in bdhelpers.c.
Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.