Cranelift: ishl.i128 with i128 shift amount panics

[bjorn3]

Steps to Reproduce

Try to compile an ishl instruction with an i128 lhs and rhs using the x64 backend.

Expected Results

It compiles.

Actual Results

Panics with thread 'rustc' panicked at 'Multi-register value not expected', /home/bjorn/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/df6812b/cranelift/codegen/src/isa/x64/lower.rs:128:10

Versions and Environment

Cranelift version or commit: df6812b

Operating system: N/A

Architecture: x86_64

This is similar to #2672 except that the lhs is also i128 in this case.

[cfallin]

Thanks for the report!

The fix here should be pretty easy -- we can just ignore the upper register since we mask the shift amount to 7 bits anyway. Happy to review a PR for this if you want to try, or I can get to it in a bit otherwise!

[bjorn3]

It seems that the shift amount is also not properly masked for i128 lhs. I have something else I want to work on right now.

[cfallin]

It seems that the shift amount is also not properly masked for i128 lhs. I have something else I want to work on right now.

I don't think that's true, FWIW: see e.g. this test case. The masking is a bit subtle, as it happens in two parts -- the 64-bit shifts do their own implicit masking on x86, then the cmoves at the end are driven by the condition code from and amt, 64 (i.e. just bit 6, not higher bits).