Cranelift AArch64: Improve the handling of callee-saved registers#2823
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This looks great, thanks! It should be a nice optimization for functions that clobber a bunch of FP state.
Just one nit requesting a comment addition below but otherwise LGTM.
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It looks like the test failures were caused by unrelated issues - I noticed that other PRs were similarly affected. |
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CI just fixed in #2830; should be good after a rebase I think! |
SIMD & FP registers are now saved and restored in pairs, similarly to general-purpose registers. Also, only the bottom 64 bits of the registers are saved and restored (in case of non-Baldrdash ABIs), which is the requirement from the Procedure Call Standard for the Arm 64-bit Architecture. As for the callee-saved general-purpose registers, if a procedure needs to save and restore an odd number of them, it no longer uses store and load pair instructions for the last register. Copyright (c) 2021, Arm Limited.
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SIMD & FP registers are now saved and restored in pairs, similarly to general-purpose registers. Also, the fix for issue #2254 has enabled us to save and to restore only the bottom 64 bits of the registers (in case of non-Baldrdash ABIs), which is the requirement from the Procedure Call Standard for the Arm 64-bit Architecture.
As for the callee-saved general-purpose registers, if a procedure needs to save and restore an odd number of them, it no longer uses store and load pair instructions for the last register.