add riscv64 backend for cranelift.#4271
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@cfallin I think we are ready. |
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I think you could do the same that for s390x, i.e. calling You can find a RISC-V example in |
still look a little hard to use to me. look like need use |
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@cfallin what do you think appropriate to solve |
If we want to wait for stabilization of the feature-detection macro in the standard library, I don't see anything wrong with assuming a baseline RISC-V ISA level for now (in other words, running with no features ever detected). Does this seem reasonable or would it result in important optimizations going missing? |
cfallin
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@yuyang-ok -- I went over the rest of the code and I think this looks generally fine. At least, passing all Wasm core tests indicates that this is of sufficient quality to merge, and can be refined and improved more in-tree.
I do have one minor comment below; and there's my answer to the getauxval question above. I'm not opposed to ignoring the getauxval issue for now (and simply not detecting features), if baseline RISC-V without extra ISA features is good enough to get started. And re: the below, a comment and factoring out the logic to a helper should be enough I think. Let me know once you've done this and then we can merge.
Thanks so much for the patience and hard work as we've reviewed this; I'm really excited to see it merge soon!
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cfallin
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Updates look good to me -- thanks!
I'm going to go ahead and merge this now. Thanks again @yuyang-ok -- this was a huge amount of work.
More improvements are always welcome of course, from you and others -- anyone who wants to talk about further improvements to the RISC-V backend, please feel free to join our project meeting or file issues!
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@cfallin ok,thanks. :-) |
Our submodule was accidentally reverted to an older commit as part of bytecodealliance#4271 and while it could be updated to as it was before I went ahead and updated it to `main`.
* Update spec test repo Our submodule was accidentally reverted to an older commit as part of #4271 and while it could be updated to as it was before I went ahead and updated it to `main`. * Update ignore directives and test multi-memory * Update riscv ignores
Congratulations! |
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How can I use this feature, is there documentation? |
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This work is for RISC-V not risc5. |
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I see that we have binaries riscv64gc here: https://github.com/bytecodealliance/wasmtime/releases/tag/v2.0.2 therefore It should probably work on riscv64 Linux. So I tried to install wasmtime in |
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The script at https://wasmtime.dev/install.sh hasn't been updated yet for riscv64 support. You should probably directly download the binary from https://github.com/bytecodealliance/wasmtime/releases/tag/v2.0.2. |
I am been trying to add riscv64 backend for cranelift these days.
right now I have pass all run test in filetests.
some features not implemented right now.
i128 mul div rem, all simd type and compare overflow.
some test need platform support.
like bitrev need qemu-riscv64 support bitmanip and zbkb extension (don't know how to enable it.).