Remove unreachable x64 lowerings for iadd_imm

[jameysharp]

All of the *_imm instructions are rewritten during legalization to an explicit iconst plus the general form of the operator, so backends never see them. Therefore these ISLE rules in the x64 backend can never match anything.

This came up in #4721 but is independent of that issue.

[cfallin]

Thanks!

[elliottt]

Just to close the loop, this is the legalization step that removes the _imm instructions:

wasmtime/cranelift/codegen/src/legalizer/mod.rs

Lines 176 to 245 in a916788

	InstructionData::BinaryImm64 { opcode, arg, imm } => {
	let is_signed = match opcode {
	ir::Opcode::IaddImm
	| ir::Opcode::IrsubImm
	| ir::Opcode::ImulImm
	| ir::Opcode::SdivImm
	| ir::Opcode::SremImm
	| ir::Opcode::IfcmpImm => true,
	_ => false,
	};
	let imm = imm_const(&mut pos, arg, imm, is_signed);
	let replace = pos.func.dfg.replace(inst);
	match opcode {
	// bitops
	ir::Opcode::BandImm => {
	replace.band(arg, imm);
	}
	ir::Opcode::BorImm => {
	replace.bor(arg, imm);
	}
	ir::Opcode::BxorImm => {
	replace.bxor(arg, imm);
	}
	// bitshifting
	ir::Opcode::IshlImm => {
	replace.ishl(arg, imm);
	}
	ir::Opcode::RotlImm => {
	replace.rotl(arg, imm);
	}
	ir::Opcode::RotrImm => {
	replace.rotr(arg, imm);
	}
	ir::Opcode::SshrImm => {
	replace.sshr(arg, imm);
	}
	ir::Opcode::UshrImm => {
	replace.ushr(arg, imm);
	}
	// math
	ir::Opcode::IaddImm => {
	replace.iadd(arg, imm);
	}
	ir::Opcode::IrsubImm => {
	// note: arg order reversed
	replace.isub(imm, arg);
	}
	ir::Opcode::ImulImm => {
	replace.imul(arg, imm);
	}
	ir::Opcode::SdivImm => {
	replace.sdiv(arg, imm);
	}
	ir::Opcode::SremImm => {
	replace.srem(arg, imm);
	}
	ir::Opcode::UdivImm => {
	replace.udiv(arg, imm);
	}
	ir::Opcode::UremImm => {
	replace.urem(arg, imm);
	}
	// comparisons
	ir::Opcode::IfcmpImm => {
	replace.ifcmp(arg, imm);
	}
	_ => prev_pos = pos.position(),
	};
	}