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x64: Lower bitcast, fabs, and fneg in ISLE#4729

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cfallin merged 6 commits into
bytecodealliance:mainfrom
elliottt:trevor/x64-bitcast-fabs-fneg
Aug 19, 2022
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x64: Lower bitcast, fabs, and fneg in ISLE#4729
cfallin merged 6 commits into
bytecodealliance:mainfrom
elliottt:trevor/x64-bitcast-fabs-fneg

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@elliottt elliottt commented Aug 17, 2022

Migrate the bitcast, fabs, and fneg instructions to ISLE

@github-actions github-actions Bot added cranelift Issues related to the Cranelift code generator cranelift:area:x64 Issues related to x64 codegen isle Related to the ISLE domain-specific language labels Aug 17, 2022
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Details This issue or pull request has been labeled: "cranelift", "cranelift:area:x64", "isle"

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r+ on new commits here; will approve once we resolve #4722 and rebase this


(rule (lower (has_type $F32X4 (fneg x)))
(x64_xorps x
(x64_pslld (vector_all_ones $F32X4)
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I wonder, would it be better to use a VCodeConstant here to get the appropriate MSBs-only-in-each-lane value?

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Would that be a savings over the two instructions?

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Possibly, though looking at xorps I see the basic SSE version is not reg, reg/mem but just reg, reg so it would still be a separate load; one load vs. dependent chain of two 1-cycle ops, the latter likely wins. Anyway it's an unimportant enough question that I don't care too much to investigate further :-)

@elliottt elliottt marked this pull request as ready for review August 18, 2022 20:05
@elliottt elliottt force-pushed the trevor/x64-bitcast-fabs-fneg branch from 409dbe1 to 30e2041 Compare August 18, 2022 20:07
@elliottt elliottt force-pushed the trevor/x64-bitcast-fabs-fneg branch from 30e2041 to 5537332 Compare August 18, 2022 20:09
@elliottt elliottt requested a review from cfallin August 18, 2022 21:37
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LGTM, thanks!

@cfallin cfallin merged commit 80c77da into bytecodealliance:main Aug 19, 2022
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