aarch64: Add support for the fmls instruction#5895
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This commit adds lowerings to the AArch64 backend for the `fmls` instruction which is intended to be leveraged in the relaxed-simd proposal for WebAssembly. This should hopefully allow for a teeny-bit-more efficient codegen for this operator instead of using the `fmla` instruction plus a negation instruction.
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| (vec_rrr_mod (VecALUModOp.Fmls) z x y (vector_size ty))) | ||
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| (rule 2 (lower (has_type ty @ (multi_lane _ _) (fma x (fneg y) z))) | ||
| (vec_rrr_mod (VecALUModOp.Fmls) z x y (vector_size ty))) |
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I suppose if both x and y are fneg then this can emit fmla instead of fneg+fmls, right? But I guess that's a rewrite we ought to do in the egraph optimizations instead.
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Indeed! The x64 rules actually end up implementing that (they enable sort of switching back and forth given their structure) but it wasn't as obvious to do here - x64 uses a helper that manages sinking a load as well which adds a fair number of permutations.
I'll send a follow-up which implements the egraph optimization.
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This implements comments from bytecodealliance#5895 to cancel out `fneg` operations in `fma` instructions. Additional support for `fmul` is added as well.
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This implements comments from #5895 to cancel out `fneg` operations in `fma` instructions. Additional support for `fmul` is added as well.
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This commit adds lowerings to the AArch64 backend for the
fmlsinstruction which is intended to be leveraged in the relaxed-simd proposal for WebAssembly. This should hopefully allow for a teeny-bit-more efficient codegen for this operator instead of using thefmlainstruction plus a negation instruction.