riscv64: Implement SIMD swizzle and shuffle#6515
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afonso360 merged 5 commits intoJun 6, 2023
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LGTM with the following little nitpicks. Thanks!
| ;; UImm5 Helpers | ||
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| ;; Extractor that matches a `Value` equivalent to a replicated UImm5 on all lanes. | ||
| ;; TODO: Try matching vconst here as well |
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Can you either resolve this TODO in this PR or turn it into TODO(#1234) with a reference to a follow up issue?
| (VecAMode.UnitStride (gen_const_amode n)) | ||
| (mem_flags_trusted) | ||
| (unmasked) | ||
| ty)) No newline at end of file |
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Nitpick: missing trailing newline
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👋 Hey,
This PR implements the
swizzleandshuffleinstructions in the RISC-V backend.swizzlemaps directly ontovrgatherwith a SEW of 8, so that's a fairly simple implementation. Forshufflewe have to do twovrgathersone for values in the range of the first register and the second for values in range of the second register and merge them together.I double checked the
shuffleimplementation, and it seems to match what v8 does.vrgatheris a somewhat special instruction in that it forbids the destination register from being the same as any of the source registers (including the mask register). I've modeled this as anearly_def, which seems to be correct based on what I've read from regalloc2 docs, but I'm not 100% sure.There are a few other instructions like this, but none that we have implemented yet.