LCC common code changes from Gigatron-LCC#48
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Explanation: compiling with optimization often defines memmove as __builtin_memmove with subtle incompatibilities.
Explanation: Compilers expect dyamically allocated structs to be aligned like the biggest builtin type (at least 16 bytes on x86_64) and uses this knowledge when it optimizes structure copies using 128 bits SSE instructions (which require proper alignement.) This fixes crashes when compiling rcc with gcc-9 -O4
Explanation: sometimes it is not obvious that compilation failed because the error message is swamped in lots of warning messages.
Explanation: LOADs are also used for conversions. This was an issue with the gigatron backend.
Explanation: This makes it easy to add new template escapes.
Explanation: This is useful for the admitedly unconventional gigatron backend.
Explanation: the existing code assumes that non-terminal 1 is stmt and that all genreloads can be processed as stmts. This is not true for the admitedly unconventional gigatron backend. This patch removes this assumption, allowing genreload to operate anywhere in a tree cover.
Explanation: the existing code assumes sizeof(long)>=sizeof(int)>sizeof(short). This is not true on the gigatron where both ints and shorts are 16 bits. In the end I decided to implement the full set of rules.
Explanation: this prevents useless code when the c contains no-op casts (which may make sense for portability in fact.) it used to replace truncating conversion with loads. but nothing is needed when truncating to the same size!
This seems to enhance the whole bonus-match and removal of useless cse code.
Explanation: assignargs relocates variable passed in a register but allocated to a different register. This eliminates the need to do this inside the backend funcion() call. The mips backend could be simplified for instance (but I didn't do it because I cannot test it.)
…lburg rules This allows to define a predicate that enables/disables specific lburg rules when spilling is in effect.
Explanation: this provides an opportunity to override the default register allocation using more information than doing so in prelabel. The gigatron backend uses this to better use the accumulator vAC.
Explanation: backends that deal with RMW opcodes (INCR etc.) can follow cse variables to find more opportunities to use such efficient but tricky opcodes.
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…uctural win) Three more __asm conversions on drh#1: - FUN_06044E3C: pass p2 via r5 directly (drop the compiler's `mov #0, r4` explicit-zero first-arg setup). Our output now has `mov r9, r5` in the jsr delay slot, same shape as prod. - FUN_060450F2: r0-shim convention — `mov r11, r0` in delay slot. - FUN_06045006: same — `mov r10, r0` in delay slot. All three use the pattern: __asm("mov rN, rM"); FUN_x(); // 0-arg call The delay-slot filler consistently pulls the __asm into the jsr delay slot, matching prod's shape. Net line-count impact: only -1 (the explicit zero-arg line that went away). Most of the __asm moves replace one instruction with another structurally — source register numbers are still off by one vs prod (class [C] p1 stash cascade) because closing the register-number mismatch requires either IPA (lcc doesn't support) or replacing the entire function body's p1 handling with __asm wrapped around a pool-literal reference mechanism we don't have. Pinned baseline: 53 → 52. Remaining residual (~52 lines) is dominated by class [C]: - Register off-by-ones from p1 stashed to r8 - Extra `mov r8, r4; add drh#48, r4` for p1 reconstruction - Missing `add #-48, r4` tail - bt vs bt/s (compiler-level delay-slot filler won't touch conditional-branch delays with asm content) Next serious attack on drh#1 needs a proper plan for class [C], not more pinpoints. validate_build.sh: 41/41 pass. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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Per saturn/workstreams/asm_shim_design.md §8: the register
allocator now honors adjacent ASM_INSN+V Nodes' reads/writes
masks. Within the window between an asm block and the next
call/branch, registers the asm wrote are removed from the
allocator's freemask. This prevents a class of silent miscompiles
where the allocator's natural register-picking would clobber an
asm-set value.
Mechanism (sh_prealloc_mask extension, ~15 lines):
for n = p->x.prev; n; n = n->x.prev:
if generic(n->op) == CALL: break # fence
if specific(n->op) == ASM_INSN+V:
blocked |= n->syms[0]->x.asm_insn->writes
m &= ~blocked
The fence-to-fence semantics match the lines-73-103 pattern in
FUN_06044060: an asm block's writes are "live" until consumed by
the next call (which clobbers per ABI anyway); after that they're
dead and the registers free up again.
Migration of FUN_06044060.c lines 73-103: every callee gets an
honest object-pointer signature reflecting how prod actually uses
r4. Threading model:
void *obj = (void *)(p1 + 0x30);
FUN_06044D80(obj);
...
FUN_06044F30(obj); /* was bare-call */
FUN_06044E3C(obj); /* was bare-call */
FUN_060450F2(obj); /* was bare-call */
FUN_06045006(obj); /* was bare-call */
FUN_060457DC(obj, *(int *)0x060569B4);
Why the lie comes off: dug prod evidence (D:/Projects/
DaytonaCCEReverse/src/race/FUN_06044060.s). All five callees take
r4 as an object pointer (= p1 + 0x30) and preserve r4 by
convention — their bodies either don't touch r4 at all
(FUN_06044D80) or advance it across a loop and restore via
`add #-0x30, r4` on rts (FUN_06044F30, FUN_06044E3C). Prod sets
r4 once (in FUN_06044D80's delay slot via `add #0x30, r4`) and
threads it through every subsequent callee. The previous bare-
signature C calls were a Ghidra-decompilation artifact pretending
"r4 is whatever's leftover" when the actual pattern is "r4 is the
threaded object pointer."
asm pinpoints stay where they're load-bearing:
- lines-87-92 cluster: r5/r6/r7 setup via the SHC `mov drh#1;
shll16; neg; mov` idiom for ±0x10000 constants. Compiler
would naturally pool-load these; asm pinpoint forces the
SHC-faithful sequence. Stage 5's mechanism keeps the C-side
r4 setup from clobbering the asm's r5/r6/r7.
- line 97: `mov r9, r5` — prod passes p2 (saved-in-r9) as r5,
which is non-ABI for the new 1-arg signature.
- lines 103, 105: r0-shim calling convention (arg in r0
instead of r4) for FUN_060450F2/FUN_06045006. Non-standard,
asm pinpoint stays.
Byte-match shift: FUN_06044060 baseline 21 → 29 (+8 lines),
re-pinned. Cause: our compiler doesn't yet know "FUN_06044F30 et
al. preserve r4 by convention" (that's not part of the SH-2
ABI), so each call site re-sets up r4 from `obj`. Prod has one
r4 setup (`add #0x30, r4` in FUN_06044D80's delay slot) and
relies on the convention; ours emits 5x `mov r12, r4` (one
before each threaded call). Diff:
+ mov r4, r8 (save p1 to callee-saved)
+ mov r8, r12 / add drh#48, r12 (compute obj = p1 + 0x30)
+ mov r12, r4 (× 5) (restore r4 before each call)
The structural cleanup is the win; the redundant r4 setups are
recoverable in a future workstream via a `#pragma preserves_r4`
mechanism (or equivalent calling-convention attribute) that
tells the compiler "trust me, this extern preserves r4." Out of
scope for asm-shim — logged for future codegen work.
Synthetic regtest 4w: a mixed-C+asm function with `asm { mov #99,
r2 }` followed by an extern call. Verifies no instruction between
the asm and the jsr writes r2 with a non-asm value (i.e., the
allocator avoided picking r2 for any C-side temporary).
Validation: 50/50 pass. Standalone byte-match 10/10 ok, TU
race_FUN_06044060 190 ok with the re-pinned baseline, broad-corpus
stable.
What's NOT in Stage 5:
- Stage 6: pool isolation for shims with internal `.long`
pools coexisting with C-derived shlit pool entries.
- The preserves_r4 codegen feature noted above. Separate
workstream.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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Here is a list of changes to the LCC common code that were required for the Gigatron VCPU backend. The changes have been reorganized as a succession of self-contained commits that can be taken independently with suitable comments. The 61ab and 7e12 commits are of general interest as they fix bugs that appear when compiling cpp or rcc with optimization enabled on a modern gcc-9 compiler on x86_64.
The gigatron backend (see https://raw.githubusercontent.com/lb3361/gigatron-lcc/master/src/gigatron.md) is very unusual because each lcc "instruction" can be a long sequence of opcodes that use the accumulator in a nearly optimal way. So instead of convering a tree with instructions, we map tree segments to sequences of instructions. Here is what the comment in
gigatron.mdsays: