Even in the same memory region, the cache hierarchy may be split one or more times. For example, the L3 caches may only cover half the memory region. In some sense, this may be a relevant factor for the users to consider in processor selection.
Downsides to this: extra complexity for a very tiny edge case. Unlikely to be worth implementing as part of selection logic, though potentially we might expose the processor cache structure for inspection so users who really want to fine-tune can use it for manual filtering.
Even in the same memory region, the cache hierarchy may be split one or more times. For example, the L3 caches may only cover half the memory region. In some sense, this may be a relevant factor for the users to consider in processor selection.
Downsides to this: extra complexity for a very tiny edge case. Unlikely to be worth implementing as part of selection logic, though potentially we might expose the processor cache structure for inspection so users who really want to fine-tune can use it for manual filtering.