feat(via_stack): directional NSEW ports, case-insensitive input, degenerate single-layer

[ThomasPluck]

Summary

Three changes to via_stack to support GDSFactory+ Livewire electrical routing:

• Directional ports: Replaces center-positioned bottom/top ports with {layer}_{N|S|E|W} ports at bbox edges. N/S ports span the x-extent, E/W ports span the y-extent — gives the router directional routing information for multi-layer electrical routes.
• Case-insensitive input normalization: bottom_layer/top_layer are matched case-insensitively against known BEOL names (e.g. METAL1 → Metal1). Original input casing is preserved in port labels so callers can pass connectivity-style names.
• Degenerate single-layer case: bottom_layer == top_layer now produces a single metal rectangle with NSEW ports instead of raising ValueError. This lets the build pipeline use via_stack uniformly for both cross-layer and same-layer junction points.

Breaking change

Port names change from bottom/top to {layer}_{N|S|E|W} (e.g. Metal1_N, Metal2_E). Checked all callers in-tree (capacitors.py, sample_to_3d_electrical.py, LNA examples) — none reference ports by name, they only use the component as a positioned ref.

Test plan

• via_stack("Metal1", "Metal2") produces Metal1_{N,S,E,W} and Metal2_{N,S,E,W} ports at correct bbox positions
• via_stack("METAL1", "METAL2") resolves case and creates correct geometry
• via_stack("Metal1", "Metal1") produces single-layer rectangle with Metal1_{N,S,E,W} ports, no vias
• via_stack("Metal2", "Metal1") still raises ValueError
• Existing callers (capacitors.py MOM cap) unaffected — CI should confirm

Summary by Sourcery

Update via_stack to support directional NSEW electrical ports with case-insensitive layer handling and a single-layer degenerate case.

New Features:

• Expose directional NSEW electrical ports per participating layer on via_stack components using bbox-based positioning.
• Allow via_stack to create a single-layer metal rectangle with ports when bottom_layer equals top_layer.

Bug Fixes:

• Relax bottom/top layer ordering validation to permit equal layers while still rejecting inverted layer order.

Enhancements:

• Normalize bottom_layer and top_layer inputs case-insensitively against known BEOL layer names while preserving original casing for port labels.

[sourcery-ai]

Reviewer's Guide

Adds directional NSEW electrical ports to via_stack, normalizes layer name inputs case-insensitively, and supports a degenerate single-layer case without error while preserving original labels in port names.

File-Level Changes

Change	Details	Files
Introduce case-insensitive normalization of bottom_layer/top_layer while preserving original input for port labels.	Build a lowercase-to-canonical-name map from BEOL and sub-metal layer names. Store original bottom_layer/top_layer strings as bottom_port_label/top_port_label for use in port naming. Normalize bottom_layer/top_layer to canonical names via the map before computing layer order.	ihp/cells/via_stacks.py
Relax layer ordering validation to allow the degenerate single-layer via_stack case.	Change bottom/top layer index comparison from >= to > when validating BEOL order. Allow bottom_layer == top_layer to pass validation and proceed to geometry creation.	ihp/cells/via_stacks.py
Replace single center 'bottom'/'top' ports with directional NSEW ports per participating layer, sized and placed at the component bounding box edges.	Remove existing center-based 'bottom' and 'top' electrical ports. Compute half-width/half-height and define NSEW port positions, orientations, and widths based on bbox extents. Build a list of participating layers that includes bottom_layer and, conditionally, top_layer if it differs in canonical or label form. Add NSEW electrical ports for each participating layer, naming them as '{original_input_label}_{direction}' and mapping to the appropriate pin layer. Ensure single-layer via_stack produces only one set of NSEW ports without vias while preserving label casing.	ihp/cells/via_stacks.py

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[sourcery-ai]

Hey - I've left some high level feedback:

• In the degenerate single-layer case, when bottom_layer and top_layer differ only by case (e.g. METAL1 vs Metal1), the current _port_layers condition still adds two sets of ports on the same physical layer; if the intent is a single set of {layer}_{N,S,E,W} ports, consider tightening the condition to only add one logical layer of ports after normalization.
• You might want to reuse the normalized layer names (bottom_layer/top_layer) consistently for port labels as well, or else clearly separate the concepts (e.g. normalized_layer vs connectivity_label) to avoid confusion where ports on the same physical layer have different naming conventions depending on input casing.

Prompt for AI Agents

Please address the comments from this code review:

## Overall Comments
- In the degenerate single-layer case, when `bottom_layer` and `top_layer` differ only by case (e.g. `METAL1` vs `Metal1`), the current `_port_layers` condition still adds two sets of ports on the same physical layer; if the intent is a single set of `{layer}_{N,S,E,W}` ports, consider tightening the condition to only add one logical layer of ports after normalization.
- You might want to reuse the normalized layer names (`bottom_layer`/`top_layer`) consistently for port labels as well, or else clearly separate the concepts (e.g. `normalized_layer` vs `connectivity_label`) to avoid confusion where ports on the same physical layer have different naming conventions depending on input casing.

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[gemini-code-assist]

Code Review

This pull request introduces case-insensitive normalization for layer names in via_stack and replaces the single "bottom" and "top" ports with directional ports (N, S, E, W) at the bounding box edges for both layers. It also relaxes the layer order check to allow the bottom and top layers to be identical. The review feedback correctly identifies a bug where duplicate overlapping ports could be created if the bottom and top layers normalize to the same physical layer but have different casings, and provides a code suggestion to resolve this.

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[gemini-code-assist]

When bottom_layer and top_layer normalize to the same physical layer but have different casings (e.g., "metal1" and "Metal1"), the condition top_port_label != bottom_port_label evaluates to True. This causes duplicate overlapping ports to be added on the same physical layer, which can lead to routing errors in gdsfactory. We should only append the top layer ports if the normalized layers are physically different.

Suggested change

	_port_layers = [(bottom_layer, bottom_port_label)]
	if top_layer != bottom_layer or top_port_label != bottom_port_label:
	_port_layers.append((top_layer, top_port_label))
	_port_layers = [(bottom_layer, bottom_port_label)]
	if top_layer != bottom_layer:
	_port_layers.append((top_layer, top_port_label))