U-Boot for iCatchtek Boards

Overview

This guide provides instructions for building and configuring U-Boot for iCatchtek boards, including details on cross-compilation, board configurations, and custom drivers.

Cross Compiler Toolchain

To build U-Boot, use the appropriate cross-compiler toolchain for your board's CPU architecture:

• For ARM Cortex-A7 (v57evb board):

  CROSS_COMPILE=/home/android_camera/iCatchtek/tool-chain10/bin/arm-icatchtek-eabi-
  export CROSS_COMPILE

• For ARM Cortex-A53 (v77p_fpga and v77p_haps100 boards):

  CROSS_COMPILE=/home/android_camera/iCatchtek/tool-chain10/bin/aarch64-icatchtek-elf-
  export CROSS_COMPILE

Linux Build Environment

Make sure your toolchain is in path of /home/android_camera/iCatchtek/tool-chain10/.

Board Configurations

Configure U-Boot for your board using the relevant defconfig file:

• v57 evb (ARM Cortex-A7): icatchtek_v57evb_defconfig
• v57p evb (ARM Cortex-A7): icatchtek_v77_evb_defconfig
• v77p fpga (ARM Cortex-A53): icatchtek_v77p_fpga_defconfig
  • load kernel from sd: icatchtek_v77p_fpga_sd_defconfig
  • load kernel from spi: icatchtek_v77p_fpga_spi_defconfig
• v77p haps100 (ARM Cortex-A53): icatchtek_v77p_haps100_defconfig
  • load kernel from spi: icatchtek_v77p_haps100_spi_defconfig
• v9-di EVB (ARM cortex-A53): icatchtek_v9_evb_defconfig
• SocG5 Zebu (ARM cortex-A55): icatchtek_socg5_zebu_defconfig

Use the following command to configure U-Boot for a specific board:

make icatchtek_v77p_haps100_defconfig

Custom Drivers

Uart Driver

U-Boot Debug UART Configuration and Baud Rate Support

The debug UART0 engine has been configured to support U-Boot logs, with enhanced baud rate support up to 460,800 bps.

Testing on HAPS100 (CA53 at 12 MHz):

In tests performed on the HAPS100 platform, using the Kermit protocol for data transfer, stable communication was achieved at a baud rate of up to 230,400 bps. The following commands illustrate the configuration for this baud rate:

=> setenv baudrate 230400
## Switching baud rate to 230400 bps and press ENTER...
=> loadb
## Ready for binary (Kermit) download to 0x40000000 at 230400 bps...

For precise baud rate settings, the FPGA with a 12 MHz clock provides a calculated baud rate based on the formula:

$$ \text{baudrate} = \frac{12000000}{\text{rounddown}\left(\frac{12000000}{\text{desired baudrate}}\right)} $$

Then, you should set 230769 in teraterm.

To start transfer, in teraterm menu of [File]->[Trasnfer]->[Kermit]->[Send...] to bring up file dialog to pick up a file.

For better experience, use gzip to zip Image to Image.gz for transferring. You could unzip it after received in U-boot.

=> loadb
## Ready for binary (kermit) download to 0x40000000 at 230400 bps...
## Total Size      = 0x002b930d = 2855693 Bytes
## Start Addr      = 0x40000000
=> unzip 0x40000000 0x50000000
Uncompressed size: 10237960 = 0x9C3808

Data Rate Performance

The following table provides an overview of achievable data rates at different baud rates, along with approximate transfer speeds and times for a 10 MB data transfer:

U-Bot baudrate	TeraTerm baudrate	Speed	Transfer Time (10 MB)
115200	115384	5 KB/s	35 minutes
230400	230769	8 KB/s	22 minutes

Clock Driver

Custom driver supporting various clock configurations. Source located in drivers/clk/icatchtek/v57clk.c. If you configure it for FPGA, the driver is drivers/clk/icatchtek/fpgaclk.c.

Now, it provides only SD and CPU clock.

MMC Driver

Custom MMC driver for enhanced support of MMC devices. Source located in drivers/mmc/icatchtek_mmc.c.

Register address is descibed in node "sd0" of DTS in arch/arm/dts/icatchtek-v77p-fpga.dts.

For print more debug information, please define LOG_DEBUG. You can find it marked in beginning of source code:

 *  Hsin-Chu, Taiwan, R.O.C.
 *
 **************************************************************************/
//#define LOG_DEBUG

#include <common.h>
#include <clk.h>
#include <cpu_func.h>

It depends on the clock driver due to global clock tree usage. However, it is currently unable to switch to 1.8V, which restricts the clock frequency to under 50MHz.

Performance of V77P on FPGA HAPS100:

=> fatload mmc 0 0x40000000 EVB.bin
4400912 bytes read in 3151 ms (1.3 MiB/s)
=> fatwrite mmc 0 0x40000000 test.bin 432710
4400912 bytes written in 3155 ms (1.3 MiB/s)

Due to HAPS100 bit file is not always routed with best performance, add "clock-frequency-div" property to manually reduce SD CRC error.

CPU driver

It displays basic CPU information and currently supports only the CA7 and CA53 architectures. The CA53 provides more detailed information than the CA7, specifically regarding the EL values. In addition to this information, the CPU commands also include "release," but we do not support that feature yet.

GPIO driver

It is basic one. It support only one group of GPIO(for example, it is now assigned pgpio in DTS)

SPI nand driver

The SPI driver located at drivers/spi/icatch_spi.c is a UCLASS_SPI driver.

Within the framework of the "spi-nand" of the UCLASS_MTD driver, it operates spi_mem_xxx functions, which invoke the operations provided by our SPI driver.

Some key points worth highlighting:

• The driver supports bus widths of 1, 2, 4, and 8 bits, with functionality verified for 1-bit and 4-bit configurations.
• A known workaround is implemented where the first page read is performed in PIO (Programmed Input/Output) mode.
• While the driver supports SPI1, it has been verified and tested only with SPI0.

MTD usage

Compatibility with iCatch SPI NAND Header

This system supports compatibility with the iCatch SPI NAND header. The flash partition mapping between iCatOs and U-Boot is as follows:

   iCatOs                  MTD
  +-------------------+   +-------------------+
  | rsvA              |   | rsvA              |
  +-------------------+   +-------------------+
  | rsvB              |   | rsvB              |
  +-------------------+   +-------------------+
  | rsvC              |   | dts               |
  +-------------------+   +-------------------+
  | diskC             |   | rootfs            |
  |                   |   |                   |
  +-------------------+   +-------------------+
  |                   |   |                   |
  | Fw1               |   | u-boot            |
  |                   |   |                   |
  +-------------------+   +-------------------+
  | free              |   | free              |
  +-------------------+   +-------------------+
  |                   |   |                   |
  | Fw2               |   | kernel            |
  |                   |   |                   |
  +-------------------+   +-------------------+

MTD Partition Information

You can view the MTD partitions using the mtd command. Below is an example of the output:

List of MTD devices:
* spi-nand0
  - device: spi_nand@0
  - parent: spi0
  - driver: spi_nand
  - path: /soc/spi0/spi_nand@0
  - type: NAND flash
  - block size: 0x20000 bytes
  - min I/O: 0x800 bytes
  - OOB size: 64 bytes
  - OOB available: 62 bytes
  - 0x000000000000-0x000008000000 : "spi-nand0"
          - 0x000000000000-0x000000040000 : "header"
          - 0x000000040000-0x0000008e0000 : "rsva"
          - 0x0000008e0000-0x000000a00000 : "rsvb"
          - 0x000000a00000-0x000000a40000 : "dtb"
          - 0x000000a40000-0x000001680000 : "rootfs"
          - 0x000001680000-0x0000020e0000 : "u-boot"
          - 0x0000020e0000-0x0000070c0000 : "free"
          - 0x0000070c0000-0x000008000000 : "kernel"

Modifying Board MTD Partitions

If you no longer need to maintain compatibility with iCatOs, you can modify the board_mtdparts_default() function.

In your updated board_mtdparts_default(), the necessary partitions include:

• dtb
• rootfs
• kernel

The order and location of these partitions do not matter.

Building U-Boot

1. Configure U-Boot:

   make icatchtek_v77p_haps100_defconfig

2. Build U-Boot:

   make

Built binaries will be in the root directory of the U-Boot source tree.

Copy u-boot.bin to download to FPGA/EVB.

Misc

memory layout

U-boot could be load to any address as CONFIG_TEXT_BASE defined.

Then it will relocate itself to the top of memory.

The Linux kernel is loaded at the beginning of memory or somewhere before stack.

+-------------------+  <- Top of Memory
|                   |
|     U-Boot.bin    |
|                   |
+-------------------+
|      Heap         |
|                   |
+-------------------+
|  Global Data Area |
|                   |
+-------------------+
|       Stack       |
|                   |
+-------------------+
|                   |  
|                   |  
|                   |  
|                   |
+-------------------+
|                   |
|                   |  
|   (Linux Kernel)  |
|                   |  
|                   |
+-------------------+  <- Start of Memory(0x40000000)

Should U-Boot.bin space Be Recycled?

The decision to recycle U-Boot.bin depends on the multi-core scenario:

• U-Boot as a Second Loader: U-Boot is loaded by the mask ROM in V57 to V77P devices.

  • U-Boot Runs on Core 0 Only:
    In this case, the other cores remain trapped in the mask ROM. It is safe to recycle U-Boot.

  • U-Boot Runs on All Cores:
    Here, Core 0 is executing while the other cores are trapped in U-Boot. Even if Core 0 jumps to the Linux kernel, you should not recycle U-Boot until all cores have transitioned to the Linux kernel. If your Linux kernel is configured to run on a single core, you can recycle U-Boot at any time.

• U-Boot as Boot Code:
  This scenario is similar to the case where U-Boot runs on all cores, as the same considerations apply.

Notice: Differences Between Mask ROM and U-Boot

• There is one important distinction between being trapped in the mask ROM and being trapped in U-Boot. Specifically, U-Boot will configure the other cores to EL2 (or EL1) in non-secure mode. This configuration allows for greater secure in managing multi-core operations compared to the mask ROM state.

FW(u-boot.bin) ISP

On FPGA

The FW is supposed to download to ROMTER. the command is:

set __COMPAT_LAYER=WINXPSP3
down.exe u-boot.bin

On V57/V57P EVB

The V57/V57P features mask ROM boot code, which consistently loads firmware according to a predefined scenario. The most common method for this process is using FRM.exe.

U-Boot is not designed to generate a download folder in a user-friendly manner. Therefore, please copy the download folder from any prebuilt project. Place the u-boot.bin file into the download folder, and then execute FRM.exe on Windows 10 or 11.

Open the Advanced page of FRM. In the left-hand side list, right-click on [Firmware], then select [Set File] to open the candidate file dialog. Choose your firmware binary file, specifically u-boot.bin.

After that, return to the Basic page and press ISP [F5] to initiate the ISP process.

U-boot porting guide

This is not a full-scale porting guide; it focuses on the necessary steps to adapt U-Boot for the V77 EVB using the existing codebase.

• Objective: To adapt U-Boot for the V77 EVB by reusing the existing V57 EVB codebase.
• Source project: V57 Evaluation Board (EVB)
• Target project: V77 Evaluation Board (EVB)

Source file	Acition	job detail
configs/icatchtek_v57evb_defconfig	copy to configs/icatchtek_v77_evb_defconfig and edit it	- CONFIG_TARGET_ICATCHTEK_V57EVB rename to CONFIG_TARGET_ICATCHTEK_V77_EVB - CONFIG_CUSTOM_SYS_INIT_SP_ADDR change to 0x40100000 - rename icatchtek-v57evb to icatchtek-v77-evb - rename icatchtek-v57evb.dts to icatchtek-v77-evb.dts - CONFIG_ICATCHTEK_V57_GPIO do not change if peri register of gpio not being changed
arch/arm/Kconfig	edit it	- Add config TARGET_ICATCHTEK_V77_EVB bool "Support icatchtek_v77_evb" select CPU_V7A select CPU select BKDOOR select ICATCHTEK_SERIAL - Add source "board/icatchtek/v77_evb/Kconfig"
arch/arm/dts/icatchtek-v57evb.dts	copy to arch/arm/dts/icatchtek-v77-evb.dts and edit it	- change header file:configs/icatchtek_v77_evb.h - change some naming - add core 2, 3 in cpus node - memory size to 1GB - sd0 pwr-gpios and cd-gpios change to fmgpio 21,22 - change phase to 0x55(value from iCatOs sd phase scan)
board/icatchtek/v57evb	clone to board/icatchtek/v77_evb	rename v57evb.* to v77_evb.*
board/icatchtek/v77_evb/Kconfig	edit it	modify every v57evb to v77_evb
board/icatchtek/v77_evb/Makefile	edit it	change v57evb.o to v77_evb.o
board/icatchtek/v77_evb/v77_evb.h	edit it	- change _V57EVB_H_ to _V77_EVB_H_ - change CHIP_ID to 6578 - add #define V57P 1 - change CPU_PHY_MPCORE to 4
board/icatchtek/v77_evb/v77_evb.c	edit it	- change header file: v77_evb.h
board/icatchtek/quart_init.S	edit it	change header file:v77_evb.h
board/icatchtek/quart_putc.S	edit it	change header file:v77_evb.h
board/icatchtek/quart_puts.S	edit it	change header file:v77_evb.h
include/configs/icatchtek_v57evb.h	copy to include/configs/icatchtek_v77_evb.h	modify __ICATCHTEK_V57EVB_H to __ICATCHTEK_V77_EVB_H
drivers/clk/icatchtek/v57clk.c	copy to drivers/clk/icatchtek/v57pclk.c	Source clocks are difference. Some of them are removed and some of them are new. Refer to http://icproject.icatchtek.com/V57P/User_Guide/GLOBAL/V57P_CUG_Clock_231130.doc. Sync hal functions by name from v57p.