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MNNVL fix#604

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chhwang merged 2 commits into
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chhwang/mnnvl
Aug 8, 2025
Merged

MNNVL fix#604
chhwang merged 2 commits into
mainfrom
chhwang/mnnvl

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@chhwang chhwang commented Aug 8, 2025

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@chhwang chhwang requested a review from Copilot August 8, 2025 04:05

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@chhwang chhwang requested a review from Copilot August 8, 2025 04:09

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@chhwang chhwang requested a review from Copilot August 8, 2025 04:12

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@chhwang chhwang requested a review from Copilot August 8, 2025 04:18

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Pull Request Overview

This PR addresses an MNNVL (Multi-Node NVLink) fix by implementing conditional CUDA NVLS support in semaphore allocation and updating CUDA IPC transport logic.

  • Adds conditional NVLS-based allocation for GPU tokens when NVLS is supported
  • Modifies CUDA IPC transport condition to be more permissive
  • Includes necessary header for GPU utilities

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.

File Description
src/semaphore.cc Adds NVLS support check and conditional allocation path for GPU tokens
src/registered_memory.cc Removes host hash requirement from CUDA IPC transport condition

Comment thread src/registered_memory.cc
Comment thread src/semaphore.cc
@chhwang chhwang enabled auto-merge (squash) August 8, 2025 19:20
@chhwang chhwang merged commit 1cc1b82 into main Aug 8, 2025
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@chhwang chhwang deleted the chhwang/mnnvl branch August 8, 2025 19:23
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3 participants