Digital_Logic_Design

CSE 315 DIGITAL LOGIC DESIGN TERM PROJECT General Info You are expected to design and implement a processor which supports instruction set: (AND,OR, ADD, LD, ST, ANDI, ORI, ADDI, XOR, XORI, JUMP, BEQ, BGT, BLT, BGE, BLE). Processor will have18 bits address width and 18 bits data width. Processor will have 5 parts as follows. Register File willhold register values and signal to write into any register. There will be 16 registers in processor.Instruction Memory will be a read-only memory and instructions will be stored in this component. Ifthe current instruction is not one of the J,BR; the next instruction will be fetched and executedconsecutively from this memory. Data Memory will be read-write memory which will store data.Program will be able to read data from data memory, and also store data to this memory. DataMemory will have 10 bits address width, and 18 bits data width. Control Unit will produce propersignals to all datapath components. For example if the instruction is ST, control unit should producememWrite signal which will allow Data Memory component to write data value on its data input tothe address on its address input. Arithmetic Logic Unit (ALU) will compute arithmetic operationsADD,OR,XOR,AND,ADDI,ORI,XORI,ANDI. Operands will be fetched from register+register or register+immediate value. Result will be stored to the Register File. Control unit should produce propersignals to ALU according to instruction opcode (Every instruction should have distinct operationalcode). Design Guide Since you already have your instructions and instruction length(18 bits), your designprocess includes; instruction set architecture and control unit design. For instruction setarchitecture you should decide on fields of your instruction like, what will be size of opcodefield? How many bits to reserve for register addressing in instruction? What is the maximumpossible size for immediate part? Control unit design will include proper signal generation forall datapath. First, you must define a Finite State Machine for your processor (Micro-programmed control unit is not allowed!). For every instruction you should decide, Howmany states an instruction will need to execute? What will be the control signals for eachstate of an instruction ? Assembly Language You should first design your instruction set architecture(ISA). Draw your ISA to thepaper by hand or by any schematic tool. When the details are clear about your processor,you can write an assembler to produce machine code input for your processor. Assemblerwill convert given mnemonics to the binary codes. You can use any programming language.In assembly language refer registers as R0,R1... R15. Logisim Design You are required to design your processor on Logisim software. Since there will bedifferent designs, you are responsible for preparing test inputs for your own processor. Youare expected to write an assembly code with all instructions defined above. Then, yourassembler will convert assembly code to machine code which will be input for your logisimdesign. You can load this machine code to the Instruction Memory by right clicking onMemory component on Logisim software. Verilog Design You are required to design your processor on Verilog HDL as final part. Eachcomponent in your design should be defined as a module in Verilog HDL. Your assemblersmachine code output will be input for your Verilog design. You are responsible forgenerating test instructions,testing debugging your design on ModelSim software.