Type
- Inconsistent with either a third-party standard (e.g. RISC-V Foundation ISA) or another OpenHW Group document.
- Spelling mistake or typo.
Location of Issue
readthedocs revision 7fca8cf
https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/control_status_registers.html
Additional context
In the table describing the CSR mstatus, the MPRV field is stated to span bits 17:16, while the official specification says it should be only bit 17. In addition, bit 12 is overlapped between an unimplemented field an the MPP field.

Type
Location of Issue
readthedocs revision 7fca8cf
https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/control_status_registers.html
Additional context
In the table describing the CSR mstatus, the MPRV field is stated to span bits 17:16, while the official specification says it should be only bit 17. In addition, bit 12 is overlapped between an unimplemented field an the MPP field.