Create cv32a6_v0.1.0_verif_KOM_minutes.md

TGs/verification-task-group/projects/CVA6/projects/cv32a6-v0.1.0-milestone/meetings/2023/cv32a6_v0.1.0_verif_KOM_minutes.md

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+Minutes of CV32A6_v0.1.0 verification kick off meeting
+
+1.	cv32a6_v0.1.0  goal
+	a.	cv32a6_v0.1.0  verification is part of CVA6 OpenHW group project. Jean-Roch Coulon is Verification technical leader and subproject manager. 
+	b.	cv32a6_v0.1.0 project aims to develop verification environment, this environment will be applied on other cva6 version, cv32a6_v0.2.0 for instance.
+	c.	Do we need to work in core-v-verif/cva6/dev branches?
+	d.	cv32a6_v0.1.0 project aims to verify “software programmer view level”.
+	e.	Current CVA6 version is 4.2. Should we rename cv32a6_v0.1.0 into cv32a6_v4.3.0 for instance ?  For information, latest tag on cva6 RTL is 4.2.0
+	f.	cv32a6_v0.2.0 and cv32a6_v0.3.0 are not granted, but they are in the roadmap.
+	g.	cv32a6_v0.1.0 project consists to adapt the existing embedded cores verification infrastructure to cv32a6_v0.1.0: specifications, dvplans, UVM agents, …  New points to be verified should be kept to be verified during next steps, cv32a6_v0.2.0 for instance.
+	h.	Functional coverage goal is not 100%, to shorten cv32a6_v0.1.0 project and keep team motivation. 100% will be reached in following projects, cv32a6_v0.2.0 for instance.
+
+2.	cv32a6_v0.1.0  plan
+	a.	Done in GANTT.
+	b.	Resources from Thales (TSS, TRT, ECC), OpenHW Group, ETHZ
+	c.	Newcomers: 10xEngineers, Bosch, Synthara,… contributions most welcome, especially to address gaps; get in touch with Jean-Roch.
+	d.	Not yet assigned tasks: MMU, A Extension, fencei, core_cntrl, linter, fix bugs, OVPSim
+	e.	Target completion date: September 2023
+
+3.	For information, SAIL provides an help to generate instruction specification.
+
+4.	User guide
+	a.	User guide should not be a copy of RISC-V International specifications but only cva6 characteristics
+	b.	Create a User guide chapter to list the cva6 parameters and detail the cv32a6_v0.1.0 configuration
+	c.	So far CV-X-IF description with cv32a6_v0.1.0 characteristics does not exist, to be specified.
+
+5.	ISS
+	a.	Spike is the cv32a6_v0.1.0 reference model
+	b.	cv32a6_v0.1.0 is open to add OVPSIM to the testbench. As cv32a6_v0.1.0 is an R&D project which does not generate profit, need to find a way to make Imperas contribution easier.
+
+6.	CVXIF
+	a.	=> The infrastructure required to verify a coprocessor needs to be pulled in CV-X-IF repository, the CV-X-IF CSEM agent for instance.
+	b.	CV-X-IF coverage should be moved outside the agent.
+
+7.	As PMA agent depends on OBI, some additional work is needed to adapt it to AXI.
+
+8.	Open question: Spike should be vendorized, or a fork ?
+
+9.	CSR
+	a.	Better to monitor CSR on RVFI tracer than on AXI, to be more agnostic.
+	b.	CSR access rights will be tested thanks to an IPXACT to test generator script. CSR HW effect to be tested are described in dedicated dvplans.
+
+10.	AXI
+	a.	AXI out of order accesses, between I and D on read access, are not covered so far, to be added.
+	b.	AXI agent should be merged soon, incremental PR will come later.
+
+11.	GitHub Issues
+	a.	To setup an homogenous way to specify the GitHub labels between different repositories, a method should be proposed by OpenHW Group staff, triage of current GitHub issues done and the method should be applied on future issues.
+	b.	To assign easily GitHub issues, an idea would be to use a Bot.
+
+12.	CI
+	a.	CI should depend on PR type: doc -> nothing, verif -> short CI, RTL -> full CI
+	b.	Provide information of Thales CI results to users in GitHub
+	c.	Add smoke tests in GitHub Actions CI
+	d.	Add Questa to smoke tests
+	e.	CI applied on cva6/master branch should be run without failing tests, CI applied on cva6/cv32a6_v0.1.0 should contain failing tests
+
+13.	Decision taken to use Verissimo to clean-up the UVM code and to use SpyGlass for RTL.
+
+14.	Decision taken to use embedded core spreadsheet to manage verification process
+
+15.	NextCloud cannot be accessed by Jérôme, to be investigated