target/riscv: implement abstract command cache#1235
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@JanMatCodasip, @MarekVCodasip, could you please take a look? |
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Thank you for this improvement. Overall, the code looks all right. I have found several things to address, though. Could you please check my comments.
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@fk-sc thank you for addressing the findings so far.
I came across few more things - if you can please look at them.
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Overall this MR looks good. I will do one last proper review tomorrow.
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Overall, this looks fine. I am sending my last batch of comments, mostly it is minor coding stuff.
I do not expect to have any more comments than that.
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@JanMatCodasip, @fk-sc, I've re-opened some of the discussions.
IMHO, the suggested improvement to abstract memory accesses should not be implemented in the same commit. Please, take a look.
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…nsupported abstract commands. It's purpose is to replace set of caching variables to one. So this commit provides one ac_not_supported_cache instead of abstract_read_csr_supported, abstract_write_csr_supported, abstract_read_fpr_supported, abstract_write_fpr_supported, has_aampostincrement. Dropped check for buggy aampostincrement Fixes riscv-collab#1232 Change-Id: I9690d9d79e3d1f593b63740b989074dcf0285637 Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
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| static bool ac_cache_contains(const struct ac_cache *cache, uint32_t command) | ||
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| return bsearch(&command, cache->commands, cache->size, |
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this MR actually adds a subtle UB , according to ubsan. cache->commands may be NULL (when cache>size == 0)
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Implemented cache of unsupported abstract commands. It's purpose is to replace set of caching variables to one. So this commit provides one ac_not_supported_cache instead of abstract_read_csr_supported,
abstract_write_csr_supported, abstract_read_fpr_supported, abstract_write_fpr_supported, has_aampostincrement.
Dropped check for buggy aampostincrement
Fixes #1232
Change-Id: I75cae1481841f2cd0393d6cc80f0d913fbe34294