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[cherry-pick] target/riscv: fix ub during instruction decode#18

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Oct 15, 2025
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[cherry-pick] target/riscv: fix ub during instruction decode#18
aap-sc merged 1 commit into
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@aap-sc aap-sc commented Oct 15, 2025

A left shift operation caused an implicit integer promotion, triggering the following UBSan error:

left shift of 254 by 24 places cannot be represented in type 'int'

NOTE: it seems that this code won't work correctly with BE targets, however this is a general problem of the whole implementation anyway.

See: riscv-collab/riscv-openocd#1299

A left shift operation caused an implicit integer promotion, triggering
the following UBSan error:

```
left shift of 254 by 24 places cannot be represented in type 'int'
```

NOTE: it seems that this code won't work correctly with BE targets,
however this is a general problem of the whole implementation anyway.

See: riscv-collab/riscv-openocd#1299

Signed-off-by: Anatoly Parshintsev <anatoly.parshintsev@syntacore.com>
@aap-sc aap-sc requested a review from en-sc October 15, 2025 18:43
@aap-sc aap-sc merged commit 25ef69e into syntacore Oct 15, 2025
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