While reviewing #9762, I realized that in the case of 32-bit operands a sign-extension is required given that cranelift-codegen, only accepts 64-bit operands.
The ARM64 documentation states 1, 2 that 32-bit operands for division are allowed.
Introducing support for 32-bit operands means that in Winch we can skip the extension sequence when dealing with 32-bit operands.
As a side note, it seems that when migrating to ISLE the intention was to add support for 32-bit operands.
cc @alexcrichton / @cfallin I'm not entirely familiar with the development history of the Aarch64 backend, is there any other reason to be aware of when considering support for 32-bit operands?
While reviewing #9762, I realized that in the case of 32-bit operands a sign-extension is required given that
cranelift-codegen, only accepts 64-bit operands.The ARM64 documentation states 1, 2 that 32-bit operands for division are allowed.
Introducing support for 32-bit operands means that in Winch we can skip the extension sequence when dealing with 32-bit operands.
As a side note, it seems that when migrating to ISLE the intention was to add support for 32-bit operands.
cc @alexcrichton / @cfallin I'm not entirely familiar with the development history of the Aarch64 backend, is there any other reason to be aware of when considering support for 32-bit operands?