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cranelift: 32bit div_s, rem_u, rem_s for aarch64#9850

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cfallin merged 8 commits into
bytecodealliance:mainfrom
MarinPostma:i32-idiv-aarch64
Dec 19, 2024
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cranelift: 32bit div_s, rem_u, rem_s for aarch64#9850
cfallin merged 8 commits into
bytecodealliance:mainfrom
MarinPostma:i32-idiv-aarch64

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@MarinPostma
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followup to #9798 where I did the ground work for 32bit division, this PR extends 32bits optimizations to rem_u, rem_s and div_s.

This should close #9766.

@MarinPostma MarinPostma requested a review from a team as a code owner December 18, 2024 12:14
@MarinPostma MarinPostma requested review from cfallin and removed request for a team December 18, 2024 12:14
@MarinPostma MarinPostma marked this pull request as draft December 18, 2024 12:42
@github-actions github-actions Bot added cranelift Issues related to the Cranelift code generator cranelift:area:aarch64 Issues related to AArch64 backend. labels Dec 18, 2024
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Looks good, thanks a bunch! Very nice to see the test expectations get shorter. A few thoughts below but nothing major.

(load_constant64_full $I64 extend n))

;; Fallback for integral 32-bit constants
(rule -1 (imm (integral_ty ty) extend n)
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Can we say (fits_in_32 ty) rather than ty here, and make this the higher-priority case (so 64-bit is the fallback)? That seems a little cleaner to me than the implicit "everything not I64 is smaller than 64 bits" here (and less likely to break if we try to do other things like support I128 more fully in the future).

ALUOp::AddS => 0b00101011_000,
ALUOp::SubS => 0b01101011_000,
ALUOp::SDiv => 0b10011010_110,
ALUOp::SDiv => 0b00011010_110,
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Can we merge the SDiv and UDiv cases now?

;; helpers for udiv:
;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
(decl put_nonzero_in_reg (Value) Reg)
;; It takes a value and entension type, and perform emits the appropriate checks.
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s/entension/extension/
s/perform/performs/

;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
(decl put_nonzero_in_reg (Value) Reg)
;; It takes a value and entension type, and perform emits the appropriate checks.
;; TODO: restore spec
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cc @avanhatt @mmcloughlin -- maybe the first instance of active work on the aarch64 backend that needs to update a spec. I definitely don't think we should block this PR on it (so don't worry about this, @MarinPostma!) but it's worth thinking what our short and medium term approaches will be to this since we're upstreamed but don't have a nice CI-integrated workflow yet -- should we keep a queue of such TODOs somewhere?

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about that: I meant to restore them at some point, but I don't know how to run the verification

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Yep, the integration with the normal dev workflow is still very much an open question; we could have you ramp up on that but I don't think it's at the point that we want to require that of everyone yet.

let value = match extend_to {
OperandSize::Size32 => {
if bits < 32 {
if *extend == generated_code::ImmExtend::Sign {
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can we make this a match (with Sign and Zero cases)?

},
OperandSize::Size64 => {
if bits < 64 {
if *extend == generated_code::ImmExtend::Sign {
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Likewise here, and we can pull the if bits < 64 in as a guard on one of the match arms as well.

if ctx.subsumes_fact_optionals(loaded_fact.as_ref(), result_fact) {
Ok(())
} else {
dbg!();
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Debugging code left in?

@MarinPostma
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MarinPostma commented Dec 18, 2024

hey @cfallin, fixing a bunch of stuff, that's why I put it in draft, but I'll include your review, as soon I manage to fix the tests :)

@github-actions github-actions Bot added the isle Related to the ISLE domain-specific language label Dec 18, 2024
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cc @cfallin, @fitzgen

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@MarinPostma MarinPostma marked this pull request as ready for review December 19, 2024 13:06
@MarinPostma MarinPostma requested a review from cfallin December 19, 2024 13:06
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Thanks!

@cfallin cfallin added this pull request to the merge queue Dec 19, 2024
Merged via the queue into bytecodealliance:main with commit a179f95 Dec 19, 2024
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winch(aarch64): Improve 32-bit {s,u}div

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