riscv64: Use Vector RegClass for Vectors#6366
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This was meant to exercise the changes in bytecodealliance#6324 but was failing in RISC-V due to some missing regalloc bits.
afonso360
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May 10, 2023
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cfallin
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Looks mostly good to me, thanks!
Just one possible improvement below but if you'd rather merge as-is and tackle it in a followup or leave as a TODO, I think that's fine too.
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👋 Hey,
This PR changes the RISC-V backend to use the new Vector Regclass when dealing with vectors. It also implements the calling convention described in this document. Essentially all vector arguments are passed via stack and all registers are caller saved.
Additionally this also adds a test for the vconst pool, which was supposed to be merged in with #6324 but was failing due to some missing ABI stuff.
I've also had to limit the maximum usable SIMD type down to 1024bits, it looks like regalloc2 does not support spills larger than 2040 bytes and it's not really worth fixing it. 1024bit vectors ought to be enough for anybody.