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riscv64: Add Newtype Wrappers for Register Classes#6459

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afonso360 merged 4 commits into
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afonso360:riscv-reg-newtypes
May 26, 2023
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riscv64: Add Newtype Wrappers for Register Classes#6459
afonso360 merged 4 commits into
bytecodealliance:mainfrom
afonso360:riscv-reg-newtypes

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@afonso360 afonso360 commented May 25, 2023

👋 Hey,

This PR is a followup to a suggestion made by @alexcrichton, it adds newtype wrappers for the different register classes that we have in the RISC-V Backend.

These are XReg, FReg and VReg, for Integer, Float and Vector. The newtypes are contained only to the ISLE layer, and do not propagate throughout the rest of the backend. However It would be a good idea to iteratively do so, I just felt that it would be too big a step for a first PR.

This change was further complicated by a rule that we have in the backend where we auto convert ValueRegs into Reg. This rule has caused issues in the past (1, 2), and was also conflicting with the newtype wrappers. Instead of adding similar rules to the newtypes, I've removed the rule and all usages of it.

Most of this change was in ext_int_if_need which returns ValueRegs, but most of its uses don't actually need more than one register. To that end I've repurposed the zext and sext rules, to act as single register zero or sign extends, and replaced the uses where only one register was necessary with those. Extends that do need multiple registers can use ext_int_if_need or extend.

These changes haven't changed any of the golden lowerings, but since it's such a broad change, I suspect we might be missing some coverage and I'm going to be fuzzing this overnight to doublecheck.

@afonso360 afonso360 requested a review from a team as a code owner May 25, 2023 18:40
@afonso360 afonso360 requested review from fitzgen and removed request for a team May 25, 2023 18:40
@github-actions github-actions Bot added cranelift Issues related to the Cranelift code generator isle Related to the ISLE domain-specific language labels May 25, 2023
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cc @cfallin, @fitzgen

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Nice!

@fitzgen fitzgen enabled auto-merge May 25, 2023 19:51
`gen_select_reg` can only compare X registers, but can move F registers based on that decision.
Adjust the type signature to reflect that.

Also add some lowering tests to cover these cases.
@afonso360 afonso360 disabled auto-merge May 25, 2023 20:19
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Can we leave this open overnight to let the fuzzer have some time to explore this? I'm not totally confident that the existing tests explore all of this. (i.e. see the latest commit about gen_select_reg)

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Fuzzing hasn't caught anything else, so I think this is probably ok to merge.

@afonso360 afonso360 added this pull request to the merge queue May 26, 2023
Merged via the queue into bytecodealliance:main with commit c8e8097 May 26, 2023
@afonso360 afonso360 deleted the riscv-reg-newtypes branch May 26, 2023 15:18
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