riscv64: Implement vector floating point rounding instructions#6920
Merged
afonso360 merged 5 commits intoAug 30, 2023
Conversation
afonso360
added
the
cranelift:area:riscv64
github-actions
Bot
added
cranelift
Subscribe to Label ActionDetailsThis issue or pull request has been labeled: "cranelift", "cranelift:area:riscv64", "isle"Thus the following users have been cc'd because of the following labels:
To subscribe or unsubscribe from this label, edit the |
afonso360
force-pushed
the
riscv-simd-float-round
branch
from
4fa1e01 to
ae39fe4
Compare
eduardomourar
pushed a commit
to eduardomourar/wasmtime
that referenced
this pull request
Sep 6, 2023
…odealliance#6920) * riscv64: Add CSR Instructions * riscv64: Add float to int vector instructions * cranelift: Split vector rounding mode tests * riscv64: Implement float rounding ops for vectors * riscv64: Update tests
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
👋 Hey,
This PR Implements the floating point rounding instructions for SIMD values in the RISC-V backend. I'm not too familiar with the intricacies of this algorithm, I've mostly just copied what LLVM emits.
This PR also re-introduces CSR Instructions (deleted in #6267). CSR's are Control and Status Registers, which are used to hold architectural state such as Floating point round modes and Vector type state, etc..
Despite being part of the Zicsr extension, this extension is part of the minimum set of extensions that we need to function (i.e. it is required for floating point to work).