riscv64: Implement SIMD floating point conversion instructions#6924
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alexcrichton
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🎊 nice!
You've done quite a lot of work on this backend and it's very much appreciated, thank you!
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…odealliance#6924) * riscv64: Implement SIMD `fvpromote_low`/`fvdemote` * riscv64: Implement SIMD `fcvt_from_{u,s}int` * riscv64: Implement SIMD `fcvt_to_{u,s}int_sat` * riscv64: Use `i8_to_imm5` constructor
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👋 Hey,
This PR implements the floating point conversion instructions (
fvdemote,fvpromote_low,fcvt_{to,from}_{u,s}int{,_sat}) on the RISC-V backend.Almost all instructions match 1-to-1 with the WASM spec, except
fcvt_to_{u,s}int_sat, where NaN's need to be manually zeroed out. And onfvdemoteRISC-V leaves the upper lanes undefined, so we also zero them out manually.🎉 With this PR we now have SIMD fully implemented for RISC-V🎉
There is 1 test that is not passing yet, but I think that is due to a NaN payload bit mismatch that is allowed by the spec. But I'm going to open a separate issue to confirm that.
(This PR is built on top of #6920 so we need to merge that one first)