Cranelift: Reassociate long and narrow chains of operations into shallow and wide trees#7466
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…low and wide trees This increases instruction-level parallelism and shrinks live ranges. It also canonicalizes into the shallow-and-wide form for reassociating constants together for cprop. Co-Authored-By: Chris Fallin <chris@cfallin.org> Co-Authored-By: Trevor Elliott <telliott@fastly.com>
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…nto shallow and wide trees (bytecodealliance#7466)" This reverts commit 72534b0. This mid-end rule was shown to be the root cause of a codegen regression in bytecodealliance#12106 and we didn't have any real examples that would improve from this rule, just a theoretical idea of its benefit. Better to do actual instruction scheduling while lowering and/or during regalloc than to do hack-y instruction scheduling in the mid-end (where we have no idea how many registers are available, for example).
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…nto shallow and wide trees (#7466)" (#12116) * Revert "Cranelift: Reassociate long and narrow chains of operations into shallow and wide trees (#7466)" This reverts commit 72534b0. This mid-end rule was shown to be the root cause of a codegen regression in #12106 and we didn't have any real examples that would improve from this rule, just a theoretical idea of its benefit. Better to do actual instruction scheduling while lowering and/or during regalloc than to do hack-y instruction scheduling in the mid-end (where we have no idea how many registers are available, for example). * update disas tests
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…nto shallow and wide trees (bytecodealliance#7466)" (bytecodealliance#12116) * Revert "Cranelift: Reassociate long and narrow chains of operations into shallow and wide trees (bytecodealliance#7466)" This reverts commit 72534b0. This mid-end rule was shown to be the root cause of a codegen regression in bytecodealliance#12106 and we didn't have any real examples that would improve from this rule, just a theoretical idea of its benefit. Better to do actual instruction scheduling while lowering and/or during regalloc than to do hack-y instruction scheduling in the mid-end (where we have no idea how many registers are available, for example). * update disas tests
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This increases instruction-level parallelism and shrinks live ranges. It also
canonicalizes into the shallow-and-wide form for reassociating constants
together for cprop.
Depends on #7456