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riscv64: Instruction selection improvements#7480

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alexcrichton merged 2 commits into
bytecodealliance:mainfrom
afonso360:riscv-add-sub
Nov 4, 2023
Merged

riscv64: Instruction selection improvements#7480
alexcrichton merged 2 commits into
bytecodealliance:mainfrom
afonso360:riscv-add-sub

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@afonso360 afonso360 commented Nov 4, 2023

👋 Hey,

This PR does two small instruction selection and encoding optimizations.

Use addi for subs

This is one of the regressions that showed up in #7468. That PR changes iadd_imm(x, -k) to isub(x, iconst(k)). We can use the same iadd instruction for both, but we didn't have a rule to do it.

So we now try to negate an Imm12 and if we are able to do that we emit an addi when subtracting.

Try to swap registers when encoding compressed instructions for commutative operations

This is pretty much the same as #7471 but for all of the remaining compressed commutative instructions.

It allows us to emit these instructions as compressed more often.

@afonso360 afonso360 added the cranelift:area:riscv64 Issues related to the RISC-V 64 backend. label Nov 4, 2023
@afonso360 afonso360 requested a review from a team as a code owner November 4, 2023 10:57
@afonso360 afonso360 requested review from cfallin and removed request for a team November 4, 2023 10:57
@github-actions github-actions Bot added the cranelift Issues related to the Cranelift code generator label Nov 4, 2023
@alexcrichton alexcrichton added this pull request to the merge queue Nov 4, 2023
Merged via the queue into bytecodealliance:main with commit aa804de Nov 4, 2023
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